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LP3905SD-A3 PDF预览

LP3905SD-A3

更新时间: 2024-11-14 04:19:55
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
15页 681K
描述
Power Management Unit For Low Power Handheld Applications

LP3905SD-A3 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:4 X 4 MM, 0.80 MM HEIGHT, LLP-14Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.29可调阈值:YES
模拟集成电路 - 其他类型:POWER SUPPLY SUPPORT CIRCUIT控制模式:VOLTAGE-MODE
JESD-30 代码:S-XDSO-N14JESD-609代码:e0
长度:4 mm湿度敏感等级:1
信道数量:2功能数量:1
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C最大输出电流:0.6 A
封装主体材料:UNSPECIFIED封装代码:HVSON
封装等效代码:SOLCC14,.16,20封装形状:SQUARE
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:0.8 mm
子类别:Switching Regulator or Controllers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.8 V
表面贴装:YES最大切换频率:2000 kHz
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:4 mmBase Number Matches:1

LP3905SD-A3 数据手册

 浏览型号LP3905SD-A3的Datasheet PDF文件第2页浏览型号LP3905SD-A3的Datasheet PDF文件第3页浏览型号LP3905SD-A3的Datasheet PDF文件第4页浏览型号LP3905SD-A3的Datasheet PDF文件第5页浏览型号LP3905SD-A3的Datasheet PDF文件第6页浏览型号LP3905SD-A3的Datasheet PDF文件第7页 
August 2006  
LP3905  
Power Management Unit For Low Power Handheld  
Applications  
General Description  
Key Specifications  
Buck Regulators  
LP3905 is  
a multi-functional Power Management Unit,  
optimized for low power handheld applications. This device  
integrates two 600mA DC/DC buck regulators and two  
150mA linear regulators. Fixed and adjustable buck output  
versions are available. The LP3905 additionally features two  
enable pins for the device output control and is offered in an  
LLP package.  
n Fixed and adjustable voltage options, range 1.0V to  
3.3V *  
n Up to 90% Efficiency  
n Auto-switching PFM-PWM mode and fixed PWM mode  
n 2MHz PWM fixed switching frequency (Typ)  
n 600mA output current  
n
4% output voltage accuracy over temp.  
Features  
n Internal softstart  
n 2.2µH inductor, 10µF Input and 10µF output Caps  
n Two buck regulators for powering high current processor  
functions or peripheral devices  
Linear Regulators  
n Output options in the range 1.5V to 3.3V *  
n 13.5µVrms output voltage noise  
n Two linear regulators for powering internal processor  
functions and I/Os  
n One enable pin for Buck1 and Linear Regulators 1 & 2  
n Separate enable pin for Buck2  
@
n PSRR - 70dB 1kHz  
n
3% output voltage accuracy over full line and load  
regulation  
n Thermal and current overload protection  
n Small 14–Pin LLP package (4mm x 4mm x 0.8mm)  
n 0mA to 150mA output current  
n Cin = 1.0µF, Cout = 0.47µF for 100mA O/P  
Cin = 1.0µF, Cout = 1.0µF for 150mA O/P  
80mV Dropout voltage  
Applications  
n Baseband Processors  
n Peripheral Processor (Video, Audio)  
n I/O Power  
* Fixed output voltage devices can be customized to fit  
system requirements. Please contact National Semiconduc-  
tor Sales Office.  
n FPGA Power  
Typical Application Circuit  
20152901  
FIGURE 1. Typical Application Circuit – 14 Pin LLP Package  
© 2006 National Semiconductor Corporation  
DS201529  
www.national.com  

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