Datasheet > LMX2492RTWR

LMX2492RTWR

更新时间： 2023-09-03 20:28:05

品牌	Logo	应用领域
德州仪器 - TI		脉冲
页数	文件大小	规格书
41页	1910K
描述
具有斜坡/线性调频脉冲生成功能的 500MHz 至 14GHz 宽带、低噪声分数 N PLL \| RTW \| 24 \| -40 to 85

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LMX2492RTWR 数据手册

LMX2492, LMX2492-Q1

ZHCSCB6 –MARCH 2014

www.ti.com.cn

Electrical Characteristics (continued)

(3.15 V ≤ Vcc ≤ 3.45 V. Vcc ≤Vcp ≤5.25 V. Typical values are at Vcc = Vcp = 3.3 V, 25 °C.

-40°C ≤ T_A≤ 85 °C for the LMX2492 and -40°C ≤ T_A≤ 125 °C for the LMX2492-Q1 ; except as specified.)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

LOGIC OUTPUT TERMINALS (MUXout,TRIG1,TRIG2,MOD)

0.8 x

Vcc

V_OH

V_OL

Output High Voltage

Output Low Voltage

Vcc

0.2 x Vcc

LOGIC INPUT TERMINALS (CE,CLK,DATA,LE,MUXout,TRIG1,TRIG2,MOD)

V_IH

Input High Voltage

Input Low Voltage

Input Leakage

1.4

Vcc

0.6

V_IL

I_IH

-5

T_CELOW

T_CEHIGH

Chip enable Low Time

Chip enable High Time

7.6 Timing Requirements, Programming Interface (CLK, DATA, LE)

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

T_CE

Clock To LE Low Time

T_CS

Data to Clock Setup Time

Data to Clock Hold Time

Clock Pulse Width High

Clock Pulse Width Low

Enable to Clock Setup Time

Enable Pulse Width High

T_CH

T_CWH

T_CWL

T_CES

T_EWH

7.7 Serial Data Input Timing

MSB

LSB

DATA

CLK

R/W

A15

CWH

CES

CWL

EWH

There are several other considerations for programming:

•

The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE

signal, the data is sent from the shift register to an actual counter.

•

If no LE signal is given after the last data bit and the clock is kept toggling, then these bits will be read into

the next lower register. This eliminates the need to send the address each time.

•

A slew rate of at least 30 V/us is recommended for the CLK, DATA, and LE signals

Timing specs also apply to readback. Readback can be done through the MUXout, TRIG1, TRIG2, or MOD

terminals.

1...3 4 567 8 9...41

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