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LMH6574MAX/NOPB PDF预览

LMH6574MAX/NOPB

更新时间: 2024-10-28 19:43:51
品牌 Logo 应用领域
美国国家半导体 - NSC 光电二极管
页数 文件大小 规格书
14页 848K
描述
IC 4-CHANNEL, VIDEO MULTIPLEXER, PDSO14, SOIC-14, Multiplexer or Switch

LMH6574MAX/NOPB 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:SSOP, SOP14,.25Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.25模拟集成电路 - 其他类型:VIDEO MULTIPLEXER
JESD-30 代码:R-PDSO-G14JESD-609代码:e3
长度:8.64 mm湿度敏感等级:1
负电源电压最大值(Vsup):-6 V负电源电压最小值(Vsup):-3 V
标称负供电电压 (Vsup):-3.3 V信道数量:4
功能数量:1端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:+-3.3/+-5 V认证状态:Not Qualified
座面最大高度:1.75 mm最大信号电流:0.02 A
子类别:Multiplexer or Switches最大供电电流 (Isup):18 mA
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:3.9 mmBase Number Matches:1

LMH6574MAX/NOPB 数据手册

 浏览型号LMH6574MAX/NOPB的Datasheet PDF文件第8页浏览型号LMH6574MAX/NOPB的Datasheet PDF文件第9页浏览型号LMH6574MAX/NOPB的Datasheet PDF文件第10页浏览型号LMH6574MAX/NOPB的Datasheet PDF文件第11页浏览型号LMH6574MAX/NOPB的Datasheet PDF文件第12页浏览型号LMH6574MAX/NOPB的Datasheet PDF文件第14页 
utmost importance to make sure that the TJMAX is never  
exceeded due to the overall power dissipation.  
Other Applications (Continued)  
Follow these steps to determine the Maximum power dissi-  
pation for the LMH6574:  
1. Calculate the quiescent (no-load) power: PAMP = ICC  
*
(VS), where VS = V+ - V.  
2. Calculate the RMS power dissipated in the output stage:  
PD (rms) = rms ((VS - VOUT) * IOUT), where VOUT and  
IOUT are the voltage across and the current through the  
external load and VS is the total supply voltage.  
3. Calculate the total RMS power: PT = PAMP + PD.  
The maximum power that the LMH6574 package can dissi-  
pate at a given temperature can be derived with the following  
equation:  
PMAX = (150˚ – TAMB)/ θJA, where TAMB = Ambient tempera-  
ture (˚C) and θJA = Thermal resistance, from junction to  
ambient, for a given package (˚C/W). For the SOIC package  
θJA is 130 ˚C/W.  
20119714  
ESD PROTECTION  
The LMH6574 is protected against electrostatic discharge  
(ESD) on all pins. The LMH6574 will survive 2000V Human  
Body model and 200V Machine model events. Under normal  
operation the ESD diodes have no effect on circuit perfor-  
mance. There are occasions, however, when the ESD di-  
odes will be evident. If the LMH6574 is driven by a large  
signal while the device is powered down the ESD diodes will  
conduct . The current that flows through the ESD diodes will  
either exit the chip through the supply pins or will flow  
through the device, hence it is possible to power up a chip  
with a large signal applied to the input pins. Using the  
shutdown mode is one way to conserve power and still  
prevent unexpected operation.  
FIGURE 8. Frequency Response vs. Capacitive Load  
LAYOUT CONSIDERATIONS  
Whenever questions about layout arise, use the evaluation  
board as a guide. The LMH730276 is the evaluation board  
supplied with samples of the LMH6574. To reduce parasitic  
capacitances, ground and power planes should be removed  
near the input and output pins. For long signal paths con-  
trolled impedance lines should be used, along with imped-  
ance matching elements at both ends. Bypass capacitors  
should be placed as close to the device as possible. Bypass  
capacitors from each rail to ground are applied in pairs. The  
larger electrolytic bypass capacitors can be located farther  
from the device, the smaller ceramic capacitors should be  
placed as close to the device as possible. In Figure 1, the  
capacitor between V+ and Vis optional, but is recom-  
mended for best second harmonic distortion. Another way to  
enhance performance is to use pairs of 0.01 µF and 0.1 µF  
ceramic capacitors for each supply bypass.  
EVALUATION BOARDS  
National Semiconductor provides the following evaluation  
boards as a guide for high frequency layout and as an aid in  
device testing and characterization. Many of the data sheet  
plots were measured with this board.  
Device  
Package  
Evaluation Board  
LMH6574  
SOIC  
LMH730276  
POWER DISSIPATION  
The LMH6574 is optimized for maximum speed and perfor-  
mance in the small form factor of the standard SOIC pack-  
age. To ensure maximum output drive and highest perfor-  
mance, thermal shutdown is not provided. Therefore, it is of  
An evaluation board can be shipped when a sample request  
is placed with National Semiconductor. Samples can be  
ordered on the National web page. (www.national.com)  
13  
www.national.com  

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