LM53600-Q1, LM53601-Q1
SNAS660D – JUNE 2015 – REVISED MAY 2021
www.ti.com
6 Pin Configuration and Functions
1
2
3
4
5
SW
GND 10
1
2
3
4
5
SW
GND 10
SYNC/
9
SYNC/
MODE
BOOT
VCC
FB
BOOT
VCC
FB
9
8
7
6
MODE
DAP
VIN
EN
8
7
6
DAP
VIN
EN
RESET
RESET
AGND
BIAS
Fixed Version
Adjustable Version
Figure 6-1. DSX Package 10-Pin WSON Top View
Table 6-1. Pin Functions
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
1
SW
P
I
Regulator switch node. Connect to output inductor.
High side gate driver upper supply rail. Connect a 100-nF capacitor from SW pin to BOOT. An internal
diode charges the capacitor while SW node is low.
2
3
BOOT
Internal 3-V regulator output. Used as supply to internal control circuits. Connect a high quality 1.0-μF
capacitor from this pin to AGND for fixed versions or to GND for adjustable versions.
VCC
P
I/P
I
FB (Fixed
Versions)
Fixed version only, this pin serves as feedback for output voltage as well as power source for VCC’s
regulator. Connect to output node. Place 10-nF bypass capacitor immediately adjacent to this pin.
4
FB (ADJ
Version)
ADJ version only, this pin serves as feedback for output voltage only. Connect to output through a
voltage divider which determines output voltage set point.
AGND (Fixed
Version)
G
P
Fixed versions only, this is the ground to which input signals and FB are compared.
5
6
BIAS (ADJ
Version)
Power source for VCC’s regulator. Connect to output node. Place 10-nF bypass capacitor immediately
adjacent to this pin.
Open drain reset output. Connect to suitable voltage supply through a current limiting pull up resistor.
High = regulator OK, Low = regulator fault. Will go low when EN = low. See Detailed Description.
RESET
O
7
8
EN
I
I
Enable input to regulator. High = on, Low = off. Can be connected to Vin. Do not float.
Input supply to regulator. Connect input bypass capacitors directly between this pin and GND.
VIN
This is a multifunction mode control input which is tolerant of voltages up to input voltage. With a valid
synchronization signal at this pin, the device will switch in forced PWM mode at the external clock
frequency and synchronize with it at the rising edge of the clock. See the Electrical Characteristics
for synchronization signal specifications. With this input tied high, the device will switch at the internal
clock frequency in forced PWM mode. With this input tied low, the device will switch at the internal
clock frequency in AUTO mode with diode emulation at light load. Spread spectrum is disabled if there
is a valid synchronization signal. Do not float.
9
SYNC/MODE
GND
I
10
G
Bypass to VIN immediately adjacent to this pin.
DAP
(EXPO
SED
Connect to ground – The sole function of the DAP interface is the thermal improvement of the device,
Thermal a direct thermal connection to a ground plane is required. The DAP is not meant as an electrical
interconnect. Electrical characteristics are not ensured.
Thermal,
GND
PAD)
(1) G = Ground, I = Input, O = Output, P = Power
Copyright © 2021 Texas Instruments Incorporated
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