LM5170
www.ti.com.cn
PIN
ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
表6-1. Pin Functions (continued)
I/O(1)
DESCRIPTION
NO.
NAME
VCCA
NC
Analog bias supply pin. Connect VCCA to VCC through an external 25-Ω resistor. A low-pass filter capacitor is
31
I/P
required from the VCCA pin to AGND.
32
No connect
—
Connect to the common source of the circuit breaker MOSFET pair. When the circuit breaker function is
disabled, simply connect to AGND through a 20-kΩresistor.
33
BRKS
O
Connect to the gate pins of the circuit breaker MOSFET pair. Once the LM5170 is enabled, an internal 330-µA
current source starts to charge the circuit breaker MOSFET gates. The BRKG to BRKS voltage is internally
clamped at 12 V.
34
35
BRKG
CSB1
O
I
CH-1 differential current sense inputs. The CSA1 pin connects to the CH-1 power inductor. The CSB1 pin
connects to the circuit breaker or directly to the LV-Port if the circuit breaker is not used. The CH-1 current sense
resistor is placed between these two current sense pins. An internal 1-MΩ resistor is connected between the
CSB1 and OVPB pins through an internal cutoff switch. During operation, the cutoff switch is closed and this
internal resistor pulls up the OVPB pins. In shutdown mode, the internal resistor is disconnected by the cutoff
switch.
36
CSA1
I
CH-1 inductor current monitor pin. A current source proportional to the CH-1 inductor current flows out of this
pin. Placing a terminating resistor and filter capacitor from IOUT1 to AGND produces a DC voltage representing
the CH-1 DC current level. An internal 25-µA offset DC current source at the IOUT1 pin raises the active signal
to be above the ground noise, thus improving the monitor noise immunity.
37
38
IOUT1
IOUT2
O
O
CH-2 inductor current monitor pin. A current proportional to the CH-2 inductor current flows out of this pin.
Placing a terminating resistor and filter capacitor from IOUT2 to AGND produces a DC voltage representing the
CH-2 DC current level. An internal 25-µA offset DC current source at the IOUT2 pin raises the active signal
above the ground noise, thus improving the monitor noise immunity.
CH-1 enable pin. Pulling EN1 above 2.4 V turns off the SS pulldown and allows CH-1 to begin a soft-start
sequence. Pulling EN1 below 1 V discharges the SS capacitor and holds it low. The high- and low-side gate
drivers of both channels are held in the low state when SS is discharged.
39
40
EN1
I
I
Input for an external clock that overrides the free-running internal oscillator. The SYNCIN pin can be left open or
grounded when it is not used.
SYNCIN
Clock output pin and fault check mode selector. SYNCOUT is connected to the downstream LM5170 in a 3- or
4-phase configuration. It also functions as a circuit breaker selection pin during start-up. Placing a 10-kΩ resistor
from the SYNCOUT to AGND pin disables the fault check feature. If no resistor is connected from SYNCOUT to
AGND, the fault check is enabled.
41
SYNCOUT
O
The PWM current programming pin. The inductor DC current level is proportional to the PWM duty cycle. Use
either ISETA or ISETD but not both for channel current programming. When ISETD is not used, short ISETD to
AGND.
42
43
ISETD
EN2
I
I
CH-2 enable pin. Pulling EN2 above 2.4 V enables CH-2. Pulling EN2 below 1 V shuts down the HO2 and LO2
drivers.
Direction command input. Pulling DIR above 2 V sets the converter to buck mode, which commands the current
to flow from the HV-Port to LV-Port. Pulling DIR below 1 V sets the converter to boost mode, which commands
the current to flow from the LV-Port to HV-Port. If the DIR pin is left open, the LM5170 detects an invalid
command and disables both channels with the MOSFET gate drivers in the low state.
44
45
DIR
I
The analog current programming pin. The inductor DC current is proportional to the ISETA voltage. Use either
I, O ISETA or ISETD but not both for channel current programming. When ISETA is not used, connect a 100-pF to
0.1-µF capacitor from ISETA to AGND.
ISETA
Analog ground reference. AGND must connect to PGND externally through a single point connection to improve
the LM5170 noise immunity.
46
47
48
AGND
OSC
DT
G
I
I
The internal oscillator frequency is programmed by a resistor between OSC and AGND.
A resistor connected between DT and AGND sets the dead time between the high-side and low-side driver
outputs. Tie the DT pin to VCCA to activate the internal adaptive dead time control.
Exposed pad of the package. No internal electrical connections. Must be soldered to the large ground plane to
reduce thermal resistance.
EP
—
—
(1) Note: G = Ground, I = Input, O = Output, P = Power
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