LM5170
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ZHCSKK1B –DECEMBER 2019 –REVISED AUGUST 2021
表6-1. Pin Functions (continued)
PIN
NAME
I/O(1)
DESCRIPTION
NO.
The inverting input of the CH-2 PWM comparator. An external RC circuit tied between VINX, RAMP2, and
AGND forms the ramp generator, producing a ramp signal proportional to the HV-Port voltage, thus achieving a
voltage feedforward function. The RAMP2 capacitor voltage is reset to AGND at the end of every switching
cycle.
8
RAMP2
OVPA
I
Connected to the non-inverting input of the HV-Port overvoltage comparator. An internal 3-MΩpullup resistor
and an external resistor across the OVPA and AGND pins form a divider that senses the HV-Port voltage. When
the OVPA pin voltage is above the 1.185-V threshold, the SS capacitor is discharged and held low until the
overvoltage condition is removed.
9
I
I
The UVLO pin serves as the master enable pin. When UVLO is pulled below 1.25 V, the entire LM5170 is in a
low quiescent current shutdown mode. When UVLO is pulled above 1.25 V but below 2.5 V, the LM5170 enters
the initialization stage where the nFAULT pin is first pulled up to 5 V, while the rest of the LM5170 is kept in the
OFF state. When UVLO is pulled above the 2.5 V, the LM5170 enters a MOSFET failure detection stage. If no
failure is detected, the circuit breaker gate driver (BRKS and BRKG) turns on, and the LM5170 enables the
oscillator and RAMP generator, and stands by until the EN1 and EN2 commands enable the channel.
10
ULVO
The output of the CH-2 transconductance (gm) error amplifier and the non-inverting input of the CH-2 PWM
comparator. A loop compensation network must be connected to this pin.
11
12
13
COMP2
SS
O
I
The soft-start programming pin. An external capacitor and an internal 25-μA current source set the ramp rate of
the COMP pins voltage during soft start. If CH-2 is enabled after CH-1 completes soft start, the CH-2 turnon is
not controlled by the SS pin.
CH-2 switch node. Connect to the CH-2 high-side MOSFET source, the low-side MOSFET drain, and the
bootstrap capacitor return terminal.
SW2
I
14
15
16
17
18
HB2
HO2
NC
P
CH-2 high-side gate driver bootstrap supply input
I/O CH-2 high-side gate driver output
No connect
I/O CH-2 low-side gate driver output
—
LO2
PGND
G
Power ground connection pin for the low-side gate drivers and external VCC bias supply
VCC bias supply pin, powering the drivers. An external bias supply between 9 V to 12 V must be applied across
the VCC and PGND pins.
19
VCC
I/P
20
21
22
23
LO1
NC
I/O CH-1 low-side gate driver output
No connect
I/O CH-1 high-side gate driver output
—
HO1
HB1
P
I
CH-1 high-side gate driver bootstrap supply input
CH-1 switch node. Connect to the CH-1 high-side MOSFET source, the low-side MOSFET drain, and the
bootstrap capacitor return terminal.
24
25
26
27
SW1
Connected to the non-inverting input of the LV-Port overvoltage comparator. An internal 1-MΩ pullup resistor
and an external resistor across the OVPB and AGND pins form the divider that senses the LV-Port voltage.
When the converter operates in boost mode, the OVPB pin status is ignored. In buck mode, when the OVPB pin
voltage is above the 1.185-V threshold, the SS capacitor is discharged and held low until the overvoltage
condition is removed.
OVPB
I
Output of the CH-1 transconductance (gm) error amplifier and the non-inverting input of the CH-1 PWM
comparator. A loop compensation network must be connected to this pin.
COMP1
nFAULT
O
Fault flag pin or external shutdown pin. When a MOSFET drain-to-source short circuit failure is detected before
start-up, the nFAULT pin is internally pulled low to report the short-circuit failure. The LM5170 remains in a
I/O disabled state. The nFAULT pin can also be externally pulled low to shut down the LM5170, serving as a forced
shutdown pin. In forced shutdown, all gate drivers turn off and nFAULT is latched low until the UVLO pin is
pulled below 1.25 V to release the latch and initiate a new start-up.
The inverting input of the CH-1 PWM comparator. An external RC circuit tied between VINX, RAMP1, and
AGND forms the ramp generator, producing a ramp signal proportional to the HV-Port voltage. This achieves a
voltage feedforward function. The RAMP1 capacitor voltage is reset to AGND at the end of every switching
28
RAMP1
I
cycle.
Multiphase configuration pin. Tied to either VCCA or AGND, the OPT pin sets the phase lag of the SYNCOUT
signal corresponding to 4-phase or 3-phase operation, respectively.
29
30
OPT
IPK
I
I
A resistor connected between IPK and AGND sets the threshold for the cycle-by-cycle current limit comparator.
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4
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