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LM1882J/883 PDF预览

LM1882J/883

更新时间: 2024-02-14 13:16:45
品牌 Logo 应用领域
德州仪器 - TI 商用集成电路
页数 文件大小 规格书
16页 236K
描述
SPECIALTY CONSUMER CIRCUIT, CDIP20, CERAMIC, DIP-20

LM1882J/883 技术参数

生命周期:Obsolete包装说明:DIP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.65商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:R-GDIP-T20长度:24.51 mm
功能数量:1端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
认证状态:Not Qualified座面最大高度:5.08 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
表面贴装:NO温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

LM1882J/883 数据手册

 浏览型号LM1882J/883的Datasheet PDF文件第3页浏览型号LM1882J/883的Datasheet PDF文件第4页浏览型号LM1882J/883的Datasheet PDF文件第5页浏览型号LM1882J/883的Datasheet PDF文件第7页浏览型号LM1882J/883的Datasheet PDF文件第8页浏览型号LM1882J/883的Datasheet PDF文件第9页 
Addressing Logic  
The register addressing logic is composed of two blocks of  
logic. The first is the address register and counter  
(ADDRCNTR), and the second is the address decode  
(ADDRDEC).  
time the High Byte is written the address counter is incre-  
mented by 1. The counter has been implemented to loop on  
the initial value loaded into the address register. For exam-  
ple: If a value of 0 was written into the address register then  
the counter would count from 0 to 18 before resetting back  
to 0. If a value of 15 was written into the address register  
then the counter would count from 15 to 18 before looping  
back to 15. If a value greater than or equal to 18 is placed  
into the address register the counter will continuously loop  
on this value. Auto addressing is initiated on the falling edge  
of LOAD when ADDRDATA is 0 and LHBYTE is 1. Incre-  
menting and loading of data registers will not commence  
until the falling edge of LOAD after ADDRDATA goes to 1.  
The next rising edge of LOAD will load the first byte of data.  
Auto Incrementing is disabled on the falling edge of LOAD  
after ADDRDATA and LHBYTE goes low.  
ADDRCNTR LOGIC  
Addresses for the data registers can be generated by one of  
two methods. Manual addressing requires that each byte of  
each register that needs to be loaded needs to be ad-  
dressed. To load both bytes of all 19 registers would require  
a total of 57 load cycles (19 address and 38 data cycles).  
Auto Addressing requires that only the initial register value  
be specified. The Auto Load sequence would require only  
39 load cycles to completely program all registers (1 ad-  
dress and 38 data cycles). In the auto load sequence the  
low order byte of the data register will be written first fol-  
lowed by the high order byte on the next load cycle. At the  
Manual Addressing Mode  
Load Falling Edge  
Ý
Cycle  
Load Rising Edge  
1
2
3
4
5
6
Enable Manual Addressing  
Enable Lbyte Data Load  
Enable Hbyte Data Load  
Enable Manual Addressing  
Enable Lbyte Data Load  
Enable Hbyte Data Load  
Load Address m  
Load Lbyte m  
Load Hbyte m  
Load Address n  
Load Lbyte n  
Load Hbyte n  
TL/F/10137–7  
Auto Addressing Mode  
Load Falling Edge  
Ý
Cycle  
Load Rising Edge  
1
2
3
4
5
6
Enable Auto Addressing  
Enable Lbyte Data Load  
Enable Hbyte Data Load  
Enable Lbyte Data Load  
Enable Hbyte Data Load  
Enable Manual Addressing  
Load Start Address n  
Load Lbyte (n)  
Load Hbyte (n); Inc Counter  
a
Load Lbyte (n 1)  
a
Load Hbyte (n 1); Inc Counter  
Load Address  
TL/F/10137–8  
6

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