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LM1882J/883 PDF预览

LM1882J/883

更新时间: 2024-02-01 12:05:06
品牌 Logo 应用领域
德州仪器 - TI 商用集成电路
页数 文件大小 规格书
16页 236K
描述
SPECIALTY CONSUMER CIRCUIT, CDIP20, CERAMIC, DIP-20

LM1882J/883 技术参数

生命周期:Obsolete包装说明:DIP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.65商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:R-GDIP-T20长度:24.51 mm
功能数量:1端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
认证状态:Not Qualified座面最大高度:5.08 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
表面贴装:NO温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

LM1882J/883 数据手册

 浏览型号LM1882J/883的Datasheet PDF文件第2页浏览型号LM1882J/883的Datasheet PDF文件第3页浏览型号LM1882J/883的Datasheet PDF文件第4页浏览型号LM1882J/883的Datasheet PDF文件第6页浏览型号LM1882J/883的Datasheet PDF文件第7页浏览型号LM1882J/883的Datasheet PDF文件第8页 
Signal Specification (Continued)  
TL/F/10137–5  
FIGURE 2A. Vertical Waveform Specification  
TL/F/1013712  
FIGURE 2B. Equalization/Serration Interval Programming  
HORIZONTAL AND VERTICAL GATING SIGNALS  
and Bit 2 of the Status Register is set to the value of 1. The  
Cursor Position generates a single pulse of n clocks wide  
during every line that the cursor is specified. The signals are  
generated by logically ORing (ANDing) the active LOW  
(HIGH) signals specified by the registers used for generat-  
ing Horizontal and Vertical Gating signals. The Vertical In-  
terrupt signal generates a pulse during the vertical interval  
specified. The Vertical Interrupt signal will change in the  
same manner as that specified for the Vertical Blanking sig-  
nal.  
Horizontal Drive and Vertical Drive outputs can be utilized  
as general purpose Gating Signals. Horizontal and Vertical  
Gating Signals are available for use when Composite Sync  
and Blank signals are selected and the value of Bit 2 of the  
Status Register is 0. The Vertical Gating signal will change  
in the same manner as that specified for the Vertical Blank.  
e
b
c
[
REG(16)  
ckper  
]
Horizontal Gating Signal Width  
REG(15)  
e
b
c
[
REG(18)  
hper  
]
Vertical Gating Signal Width  
REG(17)  
e
b
c
]
REG(15)  
[
Horizontal Cursor Width  
REG(16)  
ckper  
e
b
c
]
[
Vertical Cursor Width  
REG(18)  
REG(17)  
hper  
CURSOR POSITION AND VERTICAL INTERRUPT  
e
b
c
]
REG(13) hper  
[
Vertical Interrupt Width  
REG(14)  
The Cursor Position and Vertical Interrupt signal are avail-  
able when Composite Sync and Blank signals are selected  
5

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