Datasheet > LM1882CM

LM1882CM

更新时间： 2024-01-18 22:25:43

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
16页	343K
描述
Programmable Video Sync Generator

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技术参数
数据手册

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LM1882CM 技术参数

生命周期：	Obsolete	包装说明：	SOP,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.65	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	R-PDSO-G20	长度：	12.8 mm
功能数量：	1	端子数量：	20
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
认证状态：	Not Qualified	座面最大高度：	2.65 mm
最大压摆率：	1.6 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	表面贴装：	YES
温度等级：	MILITARY	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	7.5 mm	Base Number Matches：	1

LM1882CM 数据手册

Addressing Logic (Continued)

LOAD will load the first byte of data. Auto Incrementing is

disabled on the falling edge of LOAD after ADDRDATA and

LHBYTE goes low.

Manual Addressing Mode

Cycle #

Load Falling Edge

Load Rising Edge

Load Address m

Enable Manual Addressing

Enable Lbyte Data Load

Enable Hbyte Data Load

Enable Manual Addressing

Enable Lbyte Data Load

Enable Hbyte Data Load

Load Lbyte m

Load Hbyte m

Load Address n

Load Lbyte n

Load Hbyte n

DS100232-7

Auto Addressing Mode

Cycle #

Load Falling Edge

Load Rising Edge

Enable Auto Addressing

Load Start Address n

Enable Lbyte Data Load

Enable Hbyte Data Load

Enable Lbyte Data Load

Enable Hbyte Data Load

Enable Manual Addressing

Load Lbyte (n)

Load Hbyte (n); Inc Counter

Load Lbyte (n+1)

Load Hbyte (n+1); Inc Counter

Load Address

DS100232-8

ADDRDEC LOGIC

CLOCK is disabled. Clocking the part during a Vectored Re-

start or Vectored Clear state will have no effect on the part.

To resume operation in the new state, or disable the Vec-

tored Restart or Vectored Clear state, another

non-ADDRDEC address must be loaded. Operation will be-

gin in the new state on the rising edge of the non-ADDRDEC

load pulse. It is recommended that an unused address be

loaded following an ADDRDEC operation to prevent data

registers from accidentally being corrupted. The following

Addresses are used by the device.

The ADDRDEC logic decodes the current address and gen-

erates the enable signal for the appropriate register. The en-

able values for the registers and counters change on the fall-

ing edge of LOAD. Two types of ADDRDEC logic is enabled

by 2 pair of addresses, Addresses 22 or 54 (Vectored Re-

start logic) and Addresses 23 or 55 (Vectored Clear logic).

Loading these addresses will enable the appropriate logic

and put the part into either a Restart (all counter registers are

reinitialized with preprogrammed data) or Clear (all registers

are cleared to zero) state. Reloading the same ADDRDEC

address will not cause any change in the state of the part.

The outputs during these states are frozen and the internal

Address 0

Status Register REG0

Address 1–18Data Registers REG1–REG18

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