Datasheet > LF398MDC

LF398MDC

更新时间： 2024-01-08 19:06:26

品牌	Logo	应用领域
美国国家半导体 - NSC		放大器
页数	文件大小	规格书
13页	519K
描述
IC SAMPLE AND HOLD AMPLIFIER, 20 us ACQUISITION TIME, UUC, DIE, Sample and Hold Circuit

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LF398MDC 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	WAFER
包装说明：	DIE	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.33.00.01
风险等级：	5.56	最长采集时间：	25 µs
标称采集时间：	20 µs	放大器类型：	SAMPLE AND HOLD CIRCUIT
最大模拟输入电压：	11.5 V	最小模拟输入电压：	-11.5 V
JESD-30 代码：	X-XUUC-N	湿度敏感等级：	1
负供电电压上限：	-18 V	标称负供电电压 (Vsup)：	-15 V
功能数量：	1	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	UNSPECIFIED
封装代码：	DIE	封装等效代码：	DIE OR CHIP
封装形状：	UNSPECIFIED	封装形式：	UNCASED CHIP
峰值回流温度（摄氏度）：	260	电源：	+-15 V
认证状态：	Not Qualified	采样并保持/跟踪并保持：	SAMPLE
子类别：	Sample and Hold Circuit	最大压摆率：	6.5 mA
供电电压上限：	18 V	标称供电电压 (Vsup)：	15 V
表面贴装：	YES	技术：	BIPOLAR
温度等级：	COMMERCIAL	端子形式：	NO LEAD
端子位置：	UPPER	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

LF398MDC 数据手册

July 2000

LF198/LF298/LF398, LF198A/LF398A

Monolithic Sample-and-Hold Circuits

General Description

Features

n Operates from 5V to 18V supplies

n Less than 10 µs acquisition time

n TTL, PMOS, CMOS compatible logic input

n 0.5 mV typical hold step at C_h= 0.01 µF

n Low input offset

The LF198/LF298/LF398 are monolithic sample-and-hold

circuits which utilize BI-FET technology to obtain ultra-high

dc accuracy with fast acquisition of signal and low droop

rate. Operating as a unity gain follower, dc gain accuracy is

0.002% typical and acquisition time is as low as 6 µs to

0.01%. A bipolar input stage is used to achieve low offset

voltage and wide bandwidth. Input offset adjust is accom-

plished with a single pin, and does not degrade input offset

drift. The wide bandwidth allows the LF198 to be included in-

side the feedback loop of 1 MHz op amps without having sta-

bility problems. Input impedance of 10¹⁰Ω allows high

source impedances to be used without degrading accuracy.

n 0.002% gain accuracy

n Low output noise in hold mode

n Input characteristics do not change during hold mode

n High supply rejection ratio in sample or hold

n Wide bandwidth

n Space qualified, JM38510

P-channel junction FET’s are combined with bipolar devices

in the output amplifier to give droop rates as low as 5 mV/min

with a 1 µF hold capacitor. The JFET’s have much lower

noise than MOS devices used in previous designs and do

not exhibit high temperature instabilities. The overall design

guarantees no feed-through from input to output in the hold

mode, even for input signals equal to the supply voltages.

Logic inputs on the LF198 are fully differential with low input

current, allowing direct connection to TTL, PMOS, and

CMOS. Differential threshold is 1.4V. The LF198 will operate

from 5V to 18V supplies.

An “A” version is available with tightened electrical

specifications.

Typical Connection and Performance Curve

Acquisition Time

DS005692-32

DS005692-16

Functional Diagram

DS005692-1

DS005692

www.national.com

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