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LF398MDC PDF预览

LF398MDC

更新时间: 2024-02-10 20:43:21
品牌 Logo 应用领域
美国国家半导体 - NSC 放大器
页数 文件大小 规格书
13页 519K
描述
IC SAMPLE AND HOLD AMPLIFIER, 20 us ACQUISITION TIME, UUC, DIE, Sample and Hold Circuit

LF398MDC 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:WAFER
包装说明:DIEReach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.33.00.01
风险等级:5.56最长采集时间:25 µs
标称采集时间:20 µs放大器类型:SAMPLE AND HOLD CIRCUIT
最大模拟输入电压:11.5 V最小模拟输入电压:-11.5 V
JESD-30 代码:X-XUUC-N湿度敏感等级:1
负供电电压上限:-18 V标称负供电电压 (Vsup):-15 V
功能数量:1最高工作温度:70 °C
最低工作温度:封装主体材料:UNSPECIFIED
封装代码:DIE封装等效代码:DIE OR CHIP
封装形状:UNSPECIFIED封装形式:UNCASED CHIP
峰值回流温度(摄氏度):260电源:+-15 V
认证状态:Not Qualified采样并保持/跟踪并保持:SAMPLE
子类别:Sample and Hold Circuit最大压摆率:6.5 mA
供电电压上限:18 V标称供电电压 (Vsup):15 V
表面贴装:YES技术:BIPOLAR
温度等级:COMMERCIAL端子形式:NO LEAD
端子位置:UPPER处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

LF398MDC 数据手册

 浏览型号LF398MDC的Datasheet PDF文件第3页浏览型号LF398MDC的Datasheet PDF文件第4页浏览型号LF398MDC的Datasheet PDF文件第5页浏览型号LF398MDC的Datasheet PDF文件第7页浏览型号LF398MDC的Datasheet PDF文件第8页浏览型号LF398MDC的Datasheet PDF文件第9页 
Logic Input Configurations (Continued)  
CMOS  
7V VLOGIC (Hi State) 15V  
DS005692-35  
+
Threshold = 0.6 (V ) + 1.4V  
DS005692-36  
+
Threshold = 0.6 (V ) − 1.4V  
Op Amp Drive  
DS005692-37  
Threshold +4V  
DS005692-38  
Threshold = −4V  
Application Hints  
Hold Capacitor  
reduced if the output of the LF198 is digitized quickly after  
the hold mode is initiated. The hysteresis relaxation time  
constant in polypropylene, for instance, is 1050 ms. If  
A-to-D conversion can be made within 1 ms, hysteresis error  
will be reduced by a factor of ten.  
Hold step, acquisition time, and droop rate are the major  
trade-offs in the selection of a hold capacitor value. Size and  
cost may also become important for larger values. Use of the  
curves included with this data sheet should be helpful in se-  
lecting a reasonable value of capacitance. Keep in mind that  
for fast repetition rates or tracking fast signals, the capacitor  
drive currents may cause a significant temperature rise in  
the LF198.  
DC and AC Zeroing  
DC zeroing is accomplished by connecting the offset adjust  
pin to the wiper of a 1 kpotentiometer which has one end  
tied to V+ and the other end tied through a resistor to ground.  
The resistor should be selected to give 0.6 mA through the  
1k potentiometer.  
A significant source of error in an accurate sample and hold  
circuit is dielectric absorption in the hold capacitor. A mylar  
cap, for instance, may “sag back” up to 0.2% after a quick  
change in voltage. A long sample time is required before the  
circuit can be put back into the hold mode with this type of  
capacitor. Dielectrics with very low hysteresis are polysty-  
rene, polypropylene, and Teflon. Other types such as mica  
and polycarbonate are not nearly as good. The advantage of  
polypropylene over polystyrene is that it extends the maxi-  
mum ambient temperature from 85˚C to 100˚C. Most ce-  
AC zeroing (hold step zeroing) can be obtained by adding an  
inverter with the adjustment pot tied input to output. A 10 pF  
±
capacitor from the wiper to the hold capacitor will give 4 mV  
hold step adjustment with a 0.01 µF hold capacitor and 5V  
logic supply. For larger logic swings, a smaller capacitor  
<
(
10 pF) may be used.  
Logic Rise Time  
>
ramic capacitors are unusable with  
1% hysteresis. Ce-  
ramic “NPO” or “COG” capacitors are now available for  
125˚C operation and also have low dielectric absorption. For  
more exact data, see the curve Dielectric Absorption Error.  
The hysteresis numbers on the curve are final values, taken  
after full relaxation. The hysteresis error can be significantly  
For proper operation, logic signals into the LF198 must have  
a minimum dV/dt of 1.0 V/µs. Slower signals will cause ex-  
cessive hold step. If a R/C network is used in front of the  
www.national.com  
6

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