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LDH374A

更新时间： 2024-10-19 03:50:47
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
13页 300K
描述
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

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LDH374A 数据手册

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SN74LVCH16374A  
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
SCAS565L – MARCH 1996 – REVISED SEPTEMBER 2003  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
WidebusFamily  
Operates From 1.65 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1CLK  
1D1  
1D2  
GND  
1D3  
1D4  
2
Max t of 4.5 ns at 3.3 V  
pd  
3
4
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
5
= 3.3 V, T = 25°C  
A
6
Typical V  
(Output V  
Undershoot)  
OHV  
OH  
7
V
V
CC  
CC  
>2 V at V  
= 3.3 V, T = 25°C  
CC  
A
8
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
GND  
2D3  
2D4  
I
Supports Partial-Power-Down Mode  
off  
9
Operation  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Supports Mixed-Mode Signal Operation on  
All Ports (5-V Input and Output Voltages  
With 3.3-V V  
)
CC  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
V
V
CC  
CC  
2Q5  
2Q6  
GND  
2Q7  
2Q8  
2OE  
2D5  
2D6  
GND  
2D7  
2D8  
2CLK  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 1000-V Charged-Device Model (C101)  
description/ordering information  
This 16-bit edge-triggered D-type flip-flop is  
designed for 1.65-V to 3.6-V V  
operation.  
CC  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines  
without interface or pullup components.  
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
Tube  
SN74LVCH16374ADL  
SSOP – DL  
LVCH16374A  
Tape and reel  
Tape and reel  
Tape and reel  
SN74LVCH16374ADLR  
SN74LVCH16374ADGGR  
SN74LVCH16374ADGVR  
SN74LVCH16374AGQLR  
SN74LVCH16374AZQLR  
TSSOP – DGG  
LVCH16374A  
LDH374A  
–40°C to 85°C  
TVSOP – DGV  
VFBGA – GQL  
Tape and reel  
LDH374A  
VFBGA – ZQL (Pb-free)  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
Copyright 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

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