Datasheet > LD57100J105R

LD57100J105R

更新时间： 2022-05-14 22:22:32

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
21页	1369K
描述
1 A ultra low-dropout LDO with bias

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LD57100J105R 数据手册

LD57100

Pin configuration

Figure 3. Pin connection (top view)

VIN

V^OUT

SNS/FB

GND

VBIAS

Table 1. Pin description

Pin #

Symbol

Functions

Output voltage

Input voltage

OUT

Output voltage sense pin in fixed version. Connect to the load with a separate PCB track.

Feedback pin in adjustable version. Connect to the resistor divider central node

SNS / FB

Enable pin logic input: low = shutdown, high = active

Common ground

GND

Bias supply input

BIAS

DS13123 - Rev 5

page 3/21

1 234 5 6 7...21

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