Datasheet > LD57100J110R

LD57100J110R

更新时间： 2022-05-14 22:22:32

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
21页	1369K
描述
1 A ultra low-dropout LDO with bias

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LD57100J110R 数据手册

LD57100

Datasheet

1 A ultra low-dropout LDO with bias

Features

•

Input voltage from V_OUTto 5.5 V

Input bias supply pin from 3.0 V to 5.5 V

Ultra low-dropout voltage (40 mV typ. at 1 A load)

Low ground current (35 μA typ. at no load)

Output voltage tolerance: ±1% all over temperature range, ±0.5% at 25 °C

1 A guaranteed output current

50 mV output voltage step available from 0.4 V to 1.8 V

100 mV output voltage step available from 1.9 V to 3.6 V

Adjustable version from 0.5 V to 3.0 V

Logic-controlled electronic shutdown

Internal current limit

Thermal shutdown

Output active discharge function

Available in Flip Chip6 (0.8x1.2 mm) package

Temperature range: -40 °C to 85 °C

Applications

•

Smartphones

Product status link

Cameras

LD57100

Low voltage, low noise post regulation

Description

The LD57100 is a high accuracy voltage regulator, which provides 1 A of current. It

is equipped with an NMOS pass transistor, whose gate is biased by a dedicated pin,

thus allowing the ultra-low drop performance even at very low input voltages.

It is available in Flip Chip6 (0.8x1.2 mm), maximizing the space saving. This device

is stabilized with a small ceramic capacitor on the output. The ultra low drop, low

quiescent current and short-circuit protection make the LD57100 suitable for low

power battery-operated applications.

An enable logic control function puts the LD57100 in shutdown mode allowing a total

current consumption lower than 0.1 µA. Thermal protection is also included.

DS13123 - Rev 5 - April 2021

For further information contact your local STMicroelectronics sales office.

www.st.com

12 3 4 5 6 7...21

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