Datasheet > LC4064ZE4MN48I

LC4064ZE4MN48I

更新时间： 2024-10-28 03:02:39

品牌	Logo	应用领域
莱迪思 - LATTICE		可编程逻辑器件
页数	文件大小	规格书
54页	1258K
描述
1.8V In-System Programmable Ultra Low Power PLDs

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LC4064ZE4MN48I 数据手册

ispMACH 4000ZE Family

1.8V In-System Programmable

Ultra Low Power PLDs

August 2008

Data Sheet DS1022

■ Broad Device Offering

• 32 to 256 macrocells

Features

■ High Performance

• Multiple temperature range support

– Commercial: 0 to 90°C junction (T )

– Industrial: -40 to 105°C junction (T )

• Space-saving packages

• f

= 260MHz maximum operating frequency

MAX

• t = 4.4ns propagation delay

• Up to four global clock pins with programmable

clock polarity control

• Up to 80 PTs per output

■ Easy System Integration

• Operation with 3.3V, 2.5V, 1.8V or 1.5V

LVCMOS I/O

■ Ease of Design

• Flexible CPLD macrocells with individual clock,

reset, preset and clock enable controls

• Up to four global OE controls

• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI

interfaces

• Hot-socketing support

• Open-drain output option

• Programmable output slew rate

• 3.3V PCI compatible

• Individual local OE control per I/O pin

• Excellent First-Time-Fit^TMand reﬁt

• Wide input gating (36 input logic blocks) for fast

counters, state machines and address decoders

• I/O pins with fast setup path

• Input hysteresis*

• 1.8V core power supply

• IEEE 1149.1 boundary scan testable

• IEEE 1532 ISC compliant

■ Ultra Low Power

• Standby current as low as 10µA typical

• 1.8V core; low dynamic power

• Operational down to 1.6V V

• 1.8V In-System Programmable (ISP™) using

Boundary Scan Test Access Port (TAP)

• Pb-free package options (only)

• On-chip user oscillator and timer*

• Superior solution for power sensitive consumer

applications

• Per pin pull-up, pull-down or bus keeper

control*

• Power Guard with multiple enable signals*

*New enhanced features over original ispMACH 4000Z

Table 1. ispMACH 4000ZE Family Selection Guide

ispMACH 4032ZE

ispMACH 4064ZE

ispMACH 4128ZE

ispMACH 4256ZE

Macrocells

(ns)

4.4

4.7

128

5.8

256

5.8

t (ns)

2.2

2.5

2.9

(ns)

3.0

3.2

3.8

(MHz)

260

1.8V

241

1.8V

200

1.8V

200

1.8V

MAX

Supply Voltages (V)

Packages¹(I/O + Dedicated Inputs)

48-Pin TQFP (7 x 7mm)

64-Ball csBGA (5 x 5mm)

100-Pin TQFP (14 x 14mm)

144-Pin TQFP (20 x 20mm)

144-Ball csBGA (7 x 7mm)

1. Pb-free only.

32+4

48+4

64+10

96+4

64+10

96+14

108+4

64+10

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

DS1022_01.2

12 3 4 5 6 7...54

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与LC4064ZE4MN48I相关器件

型号	品牌	获取价格	描述	数据表
LC4064ZE4MN48IES	LATTICE	获取价格	1.8V In-System Programmable Ultra Low Power PLDs
LC4064ZE4MN64C	LATTICE	获取价格	1.8V In-System Programmable Ultra Low Power PLDs
LC4064ZE4MN64CES	LATTICE	获取价格	1.8V In-System Programmable Ultra Low Power PLDs
LC4064ZE4MN64I	LATTICE	获取价格	1.8V In-System Programmable Ultra Low Power PLDs
LC4064ZE4MN64IES	LATTICE	获取价格	1.8V In-System Programmable Ultra Low Power PLDs
LC4064ZE4TN100C	LATTICE	获取价格	1.8V In-System Programmable Ultra Low Power PLDs
LC4064ZE-4TN100C	LATTICE	获取价格	EE PLD, 4.7ns, 64-Cell, CMOS, PQFP100, 14 X 14 MM, LEAD FREE, TQFP-100
LC4064ZE4TN100CES	LATTICE	获取价格	1.8V In-System Programmable Ultra Low Power PLDs
LC4064ZE4TN100I	LATTICE	获取价格	1.8V In-System Programmable Ultra Low Power PLDs
LC4064ZE4TN100IES	LATTICE	获取价格	1.8V In-System Programmable Ultra Low Power PLDs

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