Datasheet > LAN9115

LAN9115

更新时间： 2023-12-06 20:10:41

品牌	Logo	应用领域
美国微芯 - MICROCHIP		局域网局域网（LAN）标准
页数	文件大小	规格书
114页	833K
描述
The LAN9115 is a full-featured, single-chip 10/100 Ethernet controller designed for embedded appli

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LAN9115 数据手册

LAN9115

1.1

Internal Block Overview

This section provides an overview of each of these functional blocks as shown in Figure 1-2, "Internal Block Diagram".

FIGURE 1-2:

INTERNAL BLOCK DIAGRAM

25MHz

EEPROM

(Optional)

+3.3V

3.3V to 1.8V

PLL Regulator

EEPROM

Controller

3.3V to 1.8V

Core Regulator

PME

Wakup Indicator

PLL

Power

Management

2kB to 14kB

Configurable TX FIFO

Host Bus Interface

(HBI)

10/100

LAN

Ethernet

PHY

16-bit SRAM I/F

TX Status FIFO

10/100

PIO Controller

Ethernet

RX Status FIFO

MAC

IRQ

Interrupt

Controller

MIL - RX Elastic

Buffer - 128 bytes

Optional

FIFO_SEL

2kB to 14kB

Configurable RX FIFO

External PHY - MII

Interface

MIL - TX Elastic

Buffer - 2K bytes

GP Timer

1.2

10/100 Ethernet PHY

The LAN9115 integrates an IEEE 802.3 physical layer for twisted pair Ethernet applications. The PHY can be configured

for either 100 Mbps (100Base-TX) or 10 Mbps (10Base-T) Ethernet operation in either full or half duplex configurations.

The PHY block includes auto-negotiation.

Minimal external components are required for the utilization of the Integrated PHY.

1.3

10/100 Ethernet MAC

The transmit and receive data paths are separate within the MAC allowing the highest performance especially in full

duplex mode. The data paths connect to the PIO interface Function via separate busses to increase performance. Pay-

load data as well as transmit and receive status is passed on these busses.

A third internal bus is used to access the MAC’s Control and Status Registers (CSR’s). This bus is accessible from the

host through the PIO interface function.

On the backend, the MAC interfaces with the internal 10/100 PHY through a the MII (Media Independent Interface) port

internal to the LAN9115. The MAC CSR's also provides a mechanism for accessing the PHY’s internal registers through

the internal SMI (Serial Management Interface) bus.

The Ethernet MAC can also communicate with an external PHY. This mode however, is optional.

The MAC Interface Layer (MIL), within the MAC, contains a 2K Byte transmit and a 128 Byte receive FIFO which is sep-

arate from the TX and RX FIFOs. The FIFOs within the MAC are not directly accessible from the host interface. The

differentiation between the TX/RX FIFO memory buffers and the MAC buffers is that when the transmit or receive pack-

ets are in the MAC buffers, the host no longer can control or access the TX or RX data. The MAC buffers (both TX and

RX) are in effect the working buffers of the Ethernet MAC logic. In the case of reception, the data must be moved first

to the RX FIFOs for the host to access the data. For TX operations, the MIL operates in store-and-forward mode and

will queue an entire frame before beginning transmission.

DS00002269B-page 6

 2005-2018 Microchip Technology Inc.

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与LAN9115相关器件

型号	品牌	描述	获取价格	数据表
LAN9115_05	SMSC	Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller	获取价格
LAN9115-MD	SMSC	HIGHLY EFFICIENT SINGLE - CHIP 10/100 NON PCI ETHERNET CONTROLLER	获取价格
LAN9115-MT	SMSC	HIGHLY EFFICIENT SINGLE - CHIP 10/100 NON PCI ETHERNET CONTROLLER	获取价格
LAN9116	SMSC	Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller	获取价格
LAN9116	MICROCHIP	The LAN9116 is a full-featured, single-chip 10/100 Ethernet controller designed for embedd	获取价格
LAN9116-MD	SMSC	Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller	获取价格

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