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LAN9115 PDF预览

LAN9115

更新时间: 2023-12-06 20:10:41
品牌 Logo 应用领域
美国微芯 - MICROCHIP 局域网局域网(LAN)标准
页数 文件大小 规格书
114页 833K
描述
The LAN9115 is a full-featured, single-chip 10/100 Ethernet controller designed for embedded appli

LAN9115 数据手册

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LAN9115  
Highly Efficient Single-Chip 10/100 Non-PCI  
Ethernet Controller  
• Reduced Power Modes  
Highlights  
- Numerous power management modes  
- Wake on LAN*  
- Magic packet wakeup*  
- Wakeup indicator event signal  
- Link Status Change  
• Member of LAN9118 Family; optimized for  
medium-performance applications  
• Easily interfaces to most 16-bit embedded CPU’s  
• Efficient architecture with low CPU overhead  
• Integrated PHY; supports external PHY via MII  
interface  
• Single chip Ethernet controller  
- Fully compliant with IEEE 802.3/802.3u stan-  
dards  
- Integrated Ethernet MAC and PHY  
- 10BASE-T and 100BASE-TX support  
- Full- and Half-duplex support  
- Full-duplex flow control  
• Supports audio & video streaming over Ethernet:  
multiple standard-definition (SD) MPEG2 streams  
• Medium-speed member of LAN9118 Family  
(all members are pin-compatible)  
- Backpressure for half-duplex flow control  
- Preamble generation and removal  
- Automatic 32-bit CRC generation and check-  
ing  
- Automatic payload padding and pad removal  
- Loop-back modes  
Target Applications  
• Printers, kiosks, security systems  
• General embedded applications  
• Audio distribution systems  
• Basic Cable, satellite, and IP set-top boxes  
• Video-over IP Solutions, IP PBX & Video Phones  
• Wireless routers & access points  
• Digital video recorders  
• Flexible address filtering modes  
- One 48-bit perfect address  
- 64 hash-filtered multicast addresses  
- Pass all multicast  
- Promiscuous mode  
- Inverse filtering  
Key Benefits  
- Pass all incoming with status report  
- Disable reception of broadcast packets  
• Non-PCI Ethernet controller for medium-perfor-  
mance applications  
• Integrated Ethernet PHY  
- 16-bit interface  
- Burst-mode read support  
- External MII Interface  
- Auto-negotiation  
- Automatic polarity detection and correction  
• High-Performance host bus interface  
• Eliminates dropped packets  
- Simple, SRAM-like interface  
- 16-bit data bus  
- Large, 16Kbyte FIFO memory that can be  
allocated to RX or TX functions  
- One configurable host interrupt  
- Internal SRAM can store over 200 packets  
- Supports automatic or host-triggered PAUSE  
and back-pressure flow control  
• Minimizes CPU overhead  
- Supports Slave-DMA  
- Interrupt Pin with Programmable Hold-off  
timer  
• Miscellaneous features  
- Low profile 100-pin, TQFP RoHS Compliant  
package  
- Integral 1.8V regulator  
• Reduces system cost and increases design flexi-  
bility  
- General Purpose Timer  
- SRAM-like interface easily interfaces to most  
Embedded CPU’s or SoC’s  
- Low-cost, low--pin count non-PCI interface  
for embedded designs  
- Support for optional EEPROM  
- Support for 3 status LEDs multiplexed with  
Programmable GPIO signals  
• 3.3V Power Supply with 5V tolerant I/O  
• 0 to 70C  
* Third-party brands and names are the property of their  
respective owners.  
2005-2018 Microchip Technology Inc.  
DS00002269B-page 1  

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