Datasheet > L8C202PC12

L8C202PC12

更新时间： 2024-02-04 06:12:56

品牌	Logo	应用领域
逻辑 - LOGIC		内存集成电路光电二极管先进先出芯片时钟
页数	文件大小	规格书
22页	182K
描述
512/1K/2K/4K x 9-bit Asynchronous FIFO

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中文翻译

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技术参数
数据手册

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L8C202PC12 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP, DIP28,.3	针数：	28
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.37
Is Samacsys：	N	最长访问时间：	12 ns
其他特性：	RETRANSMIT	最大时钟频率 (fCLK)：	50 MHz
周期时间：	50 ns	JESD-30 代码：	R-PDIP-T28
JESD-609代码：	e0	长度：	35.052 mm
内存密度：	9216 bit	内存集成电路类型：	OTHER FIFO
内存宽度：	9	湿度敏感等级：	3
功能数量：	1	端子数量：	28
字数：	1024 words	字数代码：	1000
工作模式：	ASYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	1KX9
输出特性：	3-STATE	可输出：	NO
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP28,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	225	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	4.572 mm
最大待机电流：	0.005 A	子类别：	FIFOs
最大压摆率：	0.15 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm	Base Number Matches：	1

L8C202PC12 数据手册

L8C201/202/203/204

DEVICES INCORPORATED

512/1K/2K/4K x 9-bit Asynchronous FIFO

L8C201/202/203/204

512/1K/2K/4K x 9-bit Asynchronous FIFO

DEVICES INCORPORATED

FEATURES

DESCRIPTION

The L8C201, L8C202, L8C203, and

L8C204 are dual-port First-In/ First-

Out (FIFO) memories. The FIFO

memory products are organized as:

The read and write operations are

internally sequential through the use

of ring pointers. No address informa-

tion is required to load and unload

data. The write operation occurs

when the Write (W) signal is LOW.

Read occurs when Read (R) goes

LOW. The nine data outputs go to the

high impedance state when R is

HIGH. Retransmit (RT) capability

allows for reset of the read pointer

when RT is pulsed LOW, allowing for

retransmission of data from the

beginning. Read Enable (R) and Write

Enable (W) must both be HIGH

during a retransmit cycle, and then R

is used to access the data. A Half-Full

(HF) output flag is available in the

single device and width expansion

modes. In the depth expansion

❑ First-In/ First-Out (FIFO) using

Dual-Port Memory

❑ Advanced CMOS Technology

❑ High Speed — to 10 ns Access Time

❑ Asynchronous and Simultaneous

L8C201 — 512 x 9-bit

L8C202 — 1024 x 9-bit

L8C203 — 2048 x 9-bit

L8C204 — 4096 x 9-bit

Read and Write

❑ Fully Expandable by both Word

Depth and/ or Bit Width

Each device utilizes a special algorithm

that loads and empties data on a first-

in/ first-out basis. Full and Empty flags

are provided to prevent data overflow

and underflow. Three additional pins

are also provided to allow for unlimited

expansion in both word size and depth.

Depth Expansion does not result in a

flow-through penalty. Multiple devices

are connected with the data and control

signals in parallel. The active device is

determined by the Expansion In (XI)

and Expansion Out (XO) signals which

are daisy chained from device to

❑ Empty and Full Warning Flags

❑ Half-Full Flag Capability

❑ Auto Retransmit Capability

❑ Package Styles Available:

• 28-pin Plastic DIP

• 32-pin Plastic LCC

• 28-pin Ceramic Flatpack

configuration, this pin provides the

Expansion Out (XO) information

which is used to tell the next FIFO that

it will be activated.

device.

L8C201/202/203/204 BLOCK DIAGRAM

These FIFOs are designed to have the

fastest data access possible. Even in

lower cycle time applications, faster

access time can eliminate timing

bottlenecks as well as leave enough

margin to allow the use of the devices

without external bus drivers.

DATA INPUTS

D8-0

WRITE

CONTROL

RAM ARRAY

512 x 9-bit

1K x 9-bit

WRITE

POINTER

READ

POINTER

The FIFOs are designed for those

applications requiring asychronous

and simultaneous read/ writes in

multiprocessing and rate buffer

applications.

2K x 9-bit

4K x 9-bit

THREE-STATE

BUFFERS

DATA OUTPUTS

8-0

READ

CONTROL

RESET

LOGIC

FL/RT

FLAG

LOGIC

EXPANSION

LOGIC

XO/HF

FIFO Products

03/04/99–LDS.8C201/2/3/4-H

12 3 4 5 6 7...22

中文翻译

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与L8C202PC12相关器件

型号	品牌	获取价格	描述	数据表
L8C202PC15	LOGIC	获取价格	512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C202PC25	LOGIC	获取价格	512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C202PI10	LOGIC	获取价格	512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C202PI12	LOGIC	获取价格	512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C202PI15	LOGIC	获取价格	512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C202PI25	LOGIC	获取价格	512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C203	LOGIC	获取价格	512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C2031KC15	LOGIC	获取价格	FIFO, 2KX9, 15ns, Asynchronous, CMOS, CQCC32, 0.450 X 0.550 INCH, CERAMIC, LCC-32
L8C2031KC25	LOGIC	获取价格	FIFO, 2KX9, 25ns, Asynchronous, CMOS, CQCC32, 0.450 X 0.550 INCH, CERAMIC, LCC-32
L8C2031KMB50	LOGIC	获取价格	FIFO, 2KX9, 50ns, Asynchronous, CMOS, CQCC32, 0.450 X 0.550 INCH, CERAMIC, LCC-32

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