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L6599D PDF预览

L6599D

更新时间: 2024-11-07 03:49:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管高压PC
页数 文件大小 规格书
36页 637K
描述
High-voltage resonant controller

L6599D 技术参数

是否Rohs认证:符合生命周期:Not Recommended
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:12 weeks风险等级:7.07
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:4392Samacsys Pin Count:16
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Small Outline Packages
Samacsys Footprint Name:ST SO-16NSamacsys Released Date:2015-04-16 09:48:08
Is Samacsys:N模拟集成电路 - 其他类型:SWITCHING CONTROLLER
控制模式:VOLTAGE-MODE控制技术:RESONANT CONTROL
最大输入电压:16 V最小输入电压:8.85 V
标称输入电压:15 VJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:9.9 mm
湿度敏感等级:3功能数量:1
端子数量:16最大输出电流:0.8 A
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:15 V认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Power Management Circuits
最大供电电流 (Isup):2 mA标称供电电压 (Vsup):15 V
表面贴装:YES切换器配置:PUSH-PULL
最大切换频率:500 kHz端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

L6599D 数据手册

 浏览型号L6599D的Datasheet PDF文件第2页浏览型号L6599D的Datasheet PDF文件第3页浏览型号L6599D的Datasheet PDF文件第4页浏览型号L6599D的Datasheet PDF文件第5页浏览型号L6599D的Datasheet PDF文件第6页浏览型号L6599D的Datasheet PDF文件第7页 
L6599  
High-voltage resonant controller  
Features  
50% duty cycle, variable frequency control of  
resonant half-bridge  
High-accuracy oscillator  
Up to 500kHz operating frequency  
DIP-16  
SO-16N  
Two-level OCP: frequency-shift and latched  
shutdown  
Order code  
Interface with PFC controller  
Latched disable input  
Part number  
Package  
Packaging  
Burst-mode operation at light load  
L6599D  
L6599TR  
L6599N  
SO-16N  
SO-16N  
DIP-16  
Tube  
Tape and reel  
Tube  
Input for power-ON/OFF sequencing or  
brownout protection  
Non-linear soft-start for monotonic output  
voltage rise  
Applications  
600V-rail compatible high-side gate driver with  
integrated bootstrap diode and high dV/dt  
immunity  
LCD & PDP TV  
Desktop PC, entry-level server  
Telecom SMPS  
-300/800mA high-side and low-side gate  
drivers with UVLO pull-down  
AC-DC adapter, open frame SMPS  
DIP-16, SO-16N packages  
Block diagram  
Vcc  
H.V.  
12  
16 VBOOT  
DISABLE  
DIS  
8
+
-
DIS  
15 HVG  
14  
S
R
Q
UV  
DETECTION  
HVG  
DRIVER  
1.85V  
5
CBOOT  
17V  
SYNCHRONOUS  
BOOTSTRAP DIODE  
UVLO  
STBY  
UVLO  
OUT  
-
LC TANK  
CIRCUIT  
STANDBY  
LEVEL  
SHIFTER  
+
1.25V  
Vs  
DRIVING  
LOGIC  
Ifmin  
11 LVG  
DEAD  
TIME  
LVG DRIVER  
+
-
2V  
10  
RFmin  
Css  
4
1
+
ISEN_DIS  
GND  
Q
S
-
1.5V  
R
UVLO  
6
ISEN  
+
-
0.8V  
CONTROL  
LOGIC  
9
PFC_STOP  
-
LINE_OK  
1.25V  
6.3V  
+
ISEN_DIS  
DIS  
STANDBY  
CF  
3
15  
µA  
VCO  
2
7
DELAY  
LINE  
May 2006  
Rev 1  
1/36  
www.st.com  
36  

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