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L21C11KMB20 PDF预览

L21C11KMB20

更新时间: 2024-11-12 21:00:51
品牌 Logo 应用领域
逻辑 - LOGIC 外围集成电路
页数 文件大小 规格书
5页 110K
描述
Pipeline Register, 8-Bit, CMOS, CQCC28, 0.450 X 0.450 INCH, CERAMIC, LCC-28

L21C11KMB20 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:QCCN,
针数:28Reach Compliance Code:unknown
ECCN代码:3A001.A.2.CHTS代码:8542.39.00.01
风险等级:5.92边界扫描:NO
外部数据总线宽度:8JESD-30 代码:S-CQCC-N28
JESD-609代码:e0长度:11.4935 mm
低功率模式:NO湿度敏感等级:3
端子数量:28最高工作温度:125 °C
最低工作温度:-55 °C输出数据总线宽度:8
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):225认证状态:Not Qualified
座面最大高度:2.54 mm最大压摆率:20 mA
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:11.4935 mm
uPs/uCs/外围集成电路类型:DSP PERIPHERAL, PIPELINE REGISTERBase Number Matches:1

L21C11KMB20 数据手册

 浏览型号L21C11KMB20的Datasheet PDF文件第2页浏览型号L21C11KMB20的Datasheet PDF文件第3页浏览型号L21C11KMB20的Datasheet PDF文件第4页浏览型号L21C11KMB20的Datasheet PDF文件第5页 
L21C11  
8-bit Variable Length Shift Register  
DEVICES INCORPORATED  
FEATURES  
DESCRIPTION  
The L21C11 is a high-speed, low  
power CMOS variable length shift  
register. It consists of a single 8-bit  
wide, adjustable length shift regis-  
ter. The shift register can be pro-  
The Length Code (L3-0) controls the  
number of delay stages applied to the  
D7-0 inputs as shown in Table 1.  
When the Length Code is 0, the input  
is delayed by 1 clock period. When  
Variable Length 8-bit Wide Shift  
Register  
Selectable Delay Length from 1 to  
16 Stages  
Low Power CMOS Technology  
Replaces TRW/Raytheon TMC2111  
Load, Shift, and Hold Instructions  
Separate Data In and Data Out Pins  
DECC SMD No. 5962-96793  
grammed to any length from 1 to 16 the Length Code is 1, the delay is 2  
stages inclusive. The length of the  
shift register is determined by the  
Length Code (L3-0) as shown in  
Table 1.  
clock periods, and so forth. The  
Length Code inputs are latched on the  
rising edge of CLK. The Length Code  
value may be changed at any time  
without affecting the contents of  
registers R1 through R15.  
Available 100% Screened to  
The data input is applied to a chain  
of registers which are clocked on the  
rising edge of the CLK input. These  
registers are numbered R1 through  
R15. A multiplexer serves to route  
the contents of any register, R1  
through R15, or the data input, D7-0,  
to the output register, denoted R16.  
Note that the minimum-length path  
from data input to output is through  
R16, consisting of a single stage of  
delay.  
MIL-STD-883, Class B  
Package Styles Available:  
• 24-pin Plastic DIP  
• 24-pin Ceramic DIP  
• 28-pin Plastic LCC, J-Lead  
• 28-pin Ceramic LCC  
L21C11 BLOCK DIAGRAM  
R15  
R14  
R13  
8
8
D7-0  
Y7-0  
R3  
R2  
R1  
4
L3-0  
CLK  
TO ALL REGISTERS  
OBSOLETE  
Pipeline Registers  
03/04/99–LDS.21C11-E  
1

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