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KM48C8000CK-5 PDF预览

KM48C8000CK-5

更新时间: 2024-11-01 20:00:39
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
20页 395K
描述
Fast Page DRAM, 8MX8, 50ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32

KM48C8000CK-5 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOJ包装说明:SOJ, SOJ32,.44
针数:32Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.92访问模式:FAST PAGE
最长访问时间:50 ns其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
I/O 类型:COMMONJESD-30 代码:R-PDSO-J32
JESD-609代码:e0长度:20.96 mm
内存密度:67108864 bit内存集成电路类型:FAST PAGE DRAM
内存宽度:8功能数量:1
端口数量:1端子数量:32
字数:8388608 words字数代码:8000000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8MX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装等效代码:SOJ32,.44
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified刷新周期:8192
座面最大高度:3.76 mm自我刷新:NO
最大待机电流:0.001 A子类别:DRAMs
最大压摆率:0.12 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10.16 mmBase Number Matches:1

KM48C8000CK-5 数据手册

 浏览型号KM48C8000CK-5的Datasheet PDF文件第2页浏览型号KM48C8000CK-5的Datasheet PDF文件第3页浏览型号KM48C8000CK-5的Datasheet PDF文件第4页浏览型号KM48C8000CK-5的Datasheet PDF文件第5页浏览型号KM48C8000CK-5的Datasheet PDF文件第6页浏览型号KM48C8000CK-5的Datasheet PDF文件第7页 
KM48C8000C,KM48C8100C  
CMOS DRAM  
8M x 8bit CMOS Dynamic RAM with Fast Page Mode  
DESCRIPTION  
This is a family of 8,388,608 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells  
within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time ( -5 or -6), package type (SOJ or TSOP-II) are optional features of  
this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. This 8Mx8 Fast Page  
Mode DRAM family is fabricated using Samsung¢s advanced CMOS process to realize high band-width, low power consumption and  
high reliability.  
• Fast Page Mode operation  
FEATURES  
• CAS-before-RAS refresh capability  
• Part Identification  
• RAS-only and Hidden refresh capability  
• Fast parallel test mode capability  
• TTL(5.0V) compatible inputs and outputs  
• Early Write or output enable controlled write  
• JEDEC Standard pinout  
- KM48C8000C(5.0V, 8K Ref.)  
- KM48C8100C(5.0V, 4K Ref.)  
Active Power Dissipation  
• Available in Plastic SOJ and TSOP(II) packages  
• +5.0V±10% power supply  
Unit : mW  
Speed  
-5  
8K  
4K  
495  
440  
660  
605  
-6  
Refresh Cycles  
Part  
NO.  
Refresh  
cycle  
Refresh time  
FUNCTIONAL BLOCK DIAGRAM  
Normal  
KM48C8000C*  
KM48C8100C  
8K  
4K  
64ms  
RAS  
CAS  
W
Vcc  
Vss  
Control  
Clocks  
VBB Generator  
* Access mode & RAS only refresh mode  
: 8K cycle/64ms  
CAS-before-RAS & Hidden refresh mode  
: 4K cycle/64ms  
Row Decoder  
Refresh Timer  
Refresh Control  
Data in  
Buffer  
Memory Array  
8,388,608 x 8  
Cells  
DQ0  
to  
DQ7  
Refresh Counter  
Row Address Buffer  
Col. Address Buffer  
Performance Range  
Speed  
Data out  
Buffer  
tRAC  
50ns  
60ns  
tCAC  
13ns  
15ns  
tRC  
tPC  
A0~A12  
(A0~A11)*1  
OE  
-5  
-6  
90ns  
110ns  
35ns  
40ns  
A0~A9  
(A0~A10)*1  
Column Decoder  
Note) *1 : 4K Refresh  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to  
change products and specifications without notice.  

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