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KM48C2000B PDF预览

KM48C2000B

更新时间: 2024-02-11 03:20:24
品牌 Logo 应用领域
三星 - SAMSUNG /
页数 文件大小 规格书
8页 82K
描述
2M x 8Bit CMOS Dynamic RAM with Fast Page Mode

KM48C2000B 数据手册

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KM48C2000B, KM48C2100B  
KM48V2000B, KM48V2100B  
CMOS DRAM  
2M x 8Bit CMOS Dynamic RAM with Fast Page Mode  
DESCRIPTION  
This is a family of 2,097,152 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells  
within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K Ref.), access time (-5,-6 or -7), power con-  
sumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-  
before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version.  
This 2Mx8 Fast Page Mode DRAM family is fabricated using Samsung's advanced CMOS process to realize high band-width, low power  
consumption and high reliability.  
It may be used as graphic memory unit for microcomputer, personal computer and portable machines.  
FEATURES  
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Fast Page Mode operation  
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Part Identification  
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Byte/Word Read/Write operation  
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CAS-before-RAS refresh capability  
- KM48C2000B/B-L (5V, 4K Ref.)  
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RAS-only and Hidden refresh capability  
Self-refresh capability (L-ver only)  
- KM48C2100B/B-L (5V, 2K Ref.)  
- KM48V2000B/B-L (3.3V, 4K Ref.)  
- KM48V2100B/B-L (3.3V, 2K Ref.)  
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Fast parallel test mode capability  
TTL(5V)/LVTTL(3.3V) compatible inputs and outputs  
Early Write or output enable controlled write  
JEDEC Standard pinout  
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Active Power Dissipation  
Unit : mW  
5V  
3.3V  
Speed  
Available in Plastic SOJ and TSOP(II) packages  
4K  
2K  
4K  
2K  
¡ ¾  
Single +5V 10% power supply (5V product)  
-5  
-6  
-7  
324  
288  
252  
396  
360  
324  
495  
440  
385  
605  
550  
495  
¡ ¾  
Single +3.3V 0.3V power supply (3.3V product)  
FUNCTIONAL BLOCK DIAGRAM  
Refresh Cycles  
RAS  
CAS  
W
Vcc  
Vss  
Part  
VCC  
NO.  
Refresh  
cycle  
Refresh period  
Control  
Clocks  
VBB Generator  
Normal  
L-ver  
C2000B  
V2000B  
C2100B  
V2100B  
5V  
3.3V  
5V  
Data in  
Buffer  
4K  
2K  
64ms  
Row Decoder  
Refresh Timer  
Refresh Control  
128ms  
32ms  
tPC  
3.3V  
DQ0  
to  
DQ7  
Memory Array  
2,097,152 x 8  
Cells  
Refresh Counter  
Row Address Buffer  
Col. Address Buffer  
Performance Range  
A0-A11  
(A0 - A10)*1  
A0 - A8  
Speed  
Remark  
tRAC  
50ns  
60ns  
70ns  
tCAC  
tRC  
Data out  
Buffer  
-5  
-6  
-7  
13ns  
90ns  
35ns 5V/3.3V  
Column Decoder  
OE  
(A0 - A9)*1  
15ns 110ns 40ns 5V/3.3V  
20ns 130ns 45ns 5V/3.3V  
Note) *1 : 2K Refresh  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to  
change products and specifications without notice.  

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