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KM44V4004CS-6 PDF预览

KM44V4004CS-6

更新时间: 2023-01-02 23:01:17
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器光电二极管
页数 文件大小 规格书
21页 384K
描述
EDO DRAM, 4MX4, 60ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, TSOP2-26/24

KM44V4004CS-6 数据手册

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KM44C4004C, KM44C4104C  
KM44V4004C, KM44V4104C  
CMOS DRAM  
4M x 4Bit CMOS Dynamic RAM with Extended Data Out  
DESCRIPTION  
This is a family of 4.194,304 x 4 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of  
memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K  
Ref.), access time (-5 or -6), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this  
family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh  
operation is available in L-version.  
This 4Mx4 EDO DRAM family is fabricated using Samsung¢s advanced CMOS process to realize high band-width, low power consump-  
tion and high reliability. It may be used as main memory unit for high level computer, microcomputer and personal computer.  
FEATURES  
Part Identification  
• Extended Data Out Mode operation  
(Fast Page Mode with Extended Data Out)  
• CAS-before-RAS refresh capability  
- KM44C4004C/C-L (5V, 4K Ref.)  
• RAS-only and Hidden refresh capability  
- KM44C4104C/C-L (5V, 2K Ref.)  
• Self-refresh capability (L-ver only)  
- KM44V4004C/C-L (3.3V, 4K Ref.)  
- KM44V4104C/C-L (3.3V, 2K Ref.)  
• Fast parallel test mode capability  
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs  
• Early Write or output enable controlled write  
• JEDEC Standard pinout  
ActivePowerDissipation  
Unit : mW  
5V  
3.3V  
• Available in Plastic SOJ and TSOP(II) packages  
• Single +5V±10% power supply (5V product)  
• Single +3.3V±0.3V power supply (3.3V product)  
Speed  
4K  
2K  
4K  
2K  
-5  
-6  
324  
288  
396  
360  
495  
440  
605  
550  
FUNCTIONAL BLOCK DIAGRAM  
Refresh Cycles  
Part  
VCC  
Refresh  
cycle  
Refresh period  
RAS  
CAS  
W
Vcc  
Vss  
Control  
Clocks  
NO.  
Normal  
L-ver  
VBB Generator  
C4004C  
V4004C  
C4104C  
V4104C  
5V  
3.3V  
5V  
4K  
2K  
64ms  
Data in  
128ms  
Buffer  
Row Decoder  
Refresh Timer  
Refresh Control  
Refresh Counter  
32ms  
3.3V  
DQ0  
to  
DQ3  
Memory Array  
4,194,304 x4  
Cells  
Performance Range  
A0-A11  
(A0 - A10) *1  
A0 - A9  
(A0 - A10) *1  
Row Address Buffer  
Col. Address Buffer  
Speed  
-5  
Remark  
tRAC  
50ns  
60ns  
tCAC  
tRC  
tHPC  
Data out  
Buffer  
Column Decoder  
OE  
15ns  
84ns  
20ns 5V/3.3V  
-6  
17ns 104ns 25ns 5V/3.3V  
Note) *1 : 2K Refresh  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to  
change products and specifications without notice.  

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