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KM44C1005DJ-5 PDF预览

KM44C1005DJ-5

更新时间: 2024-02-14 12:33:39
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
21页 407K
描述
EDO DRAM, 1MX4, 50ns, CMOS, PDSO24, 0.300 INCH, SOJ-26/24

KM44C1005DJ-5 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOJ包装说明:SOJ, SOJ24/26,.34
针数:24Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.92访问模式:FAST PAGE WITH EDO
最长访问时间:50 ns其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
I/O 类型:COMMONJESD-30 代码:R-PDSO-J24
JESD-609代码:e0长度:17.15 mm
内存密度:4194304 bit内存集成电路类型:EDO DRAM
内存宽度:4功能数量:1
端口数量:1端子数量:24
字数:1048576 words字数代码:1000000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:1MX4
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装等效代码:SOJ24/26,.34
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:5 V认证状态:Not Qualified
刷新周期:1024座面最大高度:3.76 mm
自我刷新:NO最大待机电流:0.001 A
子类别:DRAMs最大压摆率:0.085 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

KM44C1005DJ-5 数据手册

 浏览型号KM44C1005DJ-5的Datasheet PDF文件第2页浏览型号KM44C1005DJ-5的Datasheet PDF文件第3页浏览型号KM44C1005DJ-5的Datasheet PDF文件第4页浏览型号KM44C1005DJ-5的Datasheet PDF文件第5页浏览型号KM44C1005DJ-5的Datasheet PDF文件第6页浏览型号KM44C1005DJ-5的Datasheet PDF文件第7页 
KM44C1005D  
CMOS DRAM  
1M x 4bit CMOS Quad CAS DRAM with Extended Data Out  
DESCRIPTION  
This is a family of 1,048,576 x 4bit Extended Data Out Quad CAS CMOS DRAMs. Extended Data Out offers high speed random access  
of memory cells within the same row. Access time (-5, -6 or -7), power consumption(Normal), and package type (SOJ or TSOP-II) are  
optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Fur-  
thermore, Self-refresh operation is available in Low power version. Four seperate CAS pins provide for seperate I/O operation allowing  
this device to operate in parity mode. This 1Mx4 Extended Data Out DRAM family is fabricated using Samsung¢s advanced CMOS pro-  
cess to realize high band-width, low power consumption and high reliability.  
• Extended Data Out mode operation  
(Fast Page Mode with Extended data out)  
FEATURES  
• Four seperate CAS pins provide for seperate I/O  
Part Identification  
operation  
• CAS-before-RAS refresh capability  
- KM44C1005D(5V, 1K Ref.)  
• RAS-only and Hidden refresh capability  
• Self-refresh capability (L-ver only)  
• Fast parallel test mode capability  
ActivePowerDissipation  
• TTL compatible inputs and outputs  
Unit : mW  
• Early Write or output enable controlled write  
Speed  
-5  
Active power dissipation  
• JEDEC Standard pinout  
468  
413  
358  
• Available in 26(24)-pin SOJ 300mil and TSOP(II)  
300mil packages  
-6  
-7  
• Single +5V±10% power supply  
FUNCTIONAL BLOCK DIAGRAM  
Refresh Cycles  
Part  
NO.  
Refresh  
Refresh Period  
Normal  
RAS  
CAS0~3  
W
Vcc  
Vss  
Control  
Clocks  
cycle  
VBB Generator  
Row Decoder  
KM44C1005D  
1K  
16ms  
Refresh Timer  
Data in  
Buffer  
Refresh Control  
Refresh Counter  
Performance Range  
DQ0  
to  
DQ3  
Memory Array  
1,048,576 x 4  
Cells  
Speed  
tRAC  
50ns  
60ns  
70ns  
tCAC  
tRC  
tHPC  
20ns  
25ns  
30ns  
-5  
-6  
-7  
15ns  
15ns  
20ns  
84ns  
Row Address Buffer  
Col. Address Buffer  
104ns  
124ns  
Data out  
Buffer  
A0~A9  
Column Decoder  
OE  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to  
change products and specifications without notice.  

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