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KM416S8030T-GL PDF预览

KM416S8030T-GL

更新时间: 2024-11-05 12:59:15
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器
页数 文件大小 规格书
10页 120K
描述
Synchronous DRAM, 8MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54

KM416S8030T-GL 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2, TSOP54,.46,32
针数:54Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.83访问模式:FOUR BANK PAGE BURST
最长访问时间:6 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):100 MHzI/O 类型:COMMON
交错的突发长度:1,2,4,8JESD-30 代码:R-PDSO-G54
JESD-609代码:e0长度:22.22 mm
内存密度:134217728 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:16功能数量:1
端口数量:1端子数量:54
字数:8388608 words字数代码:8000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP54,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified刷新周期:4096
座面最大高度:1.2 mm自我刷新:YES
连续突发长度:1,2,4,8,FP最大待机电流:0.001 A
子类别:DRAMs最大压摆率:0.2 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10.16 mm
Base Number Matches:1

KM416S8030T-GL 数据手册

 浏览型号KM416S8030T-GL的Datasheet PDF文件第2页浏览型号KM416S8030T-GL的Datasheet PDF文件第3页浏览型号KM416S8030T-GL的Datasheet PDF文件第4页浏览型号KM416S8030T-GL的Datasheet PDF文件第5页浏览型号KM416S8030T-GL的Datasheet PDF文件第6页浏览型号KM416S8030T-GL的Datasheet PDF文件第7页 
Preliminary  
KM416S8030  
CMOS SDRAM  
2M x 16Bit x 4 Banks Synchronous DRAM  
FEATURES  
GENERAL DESCRIPTION  
• JEDEC standard 3.3V power supply  
• LVTTL compatible with multiplexed address  
• Four banks operation  
The KM416S8030 is 134,217,728 bits synchronous high data  
rate Dynamic RAM organized as 4 x 2,097,152 words by 16  
bits, fabricated with SAMSUNG¢s high performance CMOS  
technology. Synchronous design allows precise cycle control  
with the use of system clock I/O transactions are possible on  
every clcok cycle. Range of operating frequencies, programma-  
ble burst length and programmable latencies allow the same  
device to be useful for a variety of high bandwidth, high perfor-  
mance memory system applications.  
• MRS cycle with address key programs  
-. CAS Latency (2 & 3)  
-. Burst Length (1, 2, 4, 8 & full page)  
-. Burst Type (Sequential & Interleave)  
• All inputs are sampled at the positive going edge of the system  
clock.  
• Burst Read Single-bit Write operation  
• DQM for masking  
ORDERING INFORMATION  
• Auto & self refresh  
Part NO.  
MAX Freq. Interface Package  
• 64ms refresh period (4K cycle)  
KM416S8030T-G/F8  
KM416S8030T-G/FH  
KM416S8030T-G/FL  
KM416S8030T-G/F10  
125MHz  
54pin  
TSOP(II)  
100MHz  
100MHz  
100MHz  
LVTTL  
FUNCTIONAL BLOCK DIAGRAM  
LWE  
Data Input Register  
LDQM  
Bank Select  
2M x 16  
2M x 16  
2M x 16  
2M x 16  
DQi  
CLK  
ADD  
Column Decoder  
Latency & Burst Length  
LCKE  
Programming Register  
LWCBR  
LRAS  
LCBR  
LWE  
LCAS  
LDQM  
Timing Register  
CLK  
CKE  
CS  
RAS  
CAS  
WE  
LDQM  
UDQM  
Samsung Electronics reserves the right to  
change products or specification without  
notice.  
*
REV. 2 Mar. '98  

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