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K7D401871-H22 PDF预览

K7D401871-H22

更新时间: 2024-11-09 19:54:31
品牌 Logo 应用领域
三星 - SAMSUNG 静态存储器内存集成电路
页数 文件大小 规格书
13页 315K
描述
Standard SRAM, 256KX18, 2.4ns, CMOS, PBGA153, 14 X 22 MM, BGA-153

K7D401871-H22 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:BGA,针数:153
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:2.4 ns其他特性:ALSO REQUIRES 1.5V I/O SUPPLY
JESD-30 代码:R-PBGA-B153长度:22 mm
内存密度:4718592 bit内存集成电路类型:STANDARD SRAM
内存宽度:18功能数量:1
端子数量:153字数:262144 words
字数代码:256000工作模式:SYNCHRONOUS
组织:256KX18封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:RECTANGULAR
封装形式:GRID ARRAY并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:2.21 mm
最大供电电压 (Vsup):2.6 V最小供电电压 (Vsup):2.4 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
宽度:14 mmBase Number Matches:1

K7D401871-H22 数据手册

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ADVANCE  
128Kx36 & 256Kx18 SRAM  
K7D403671  
K7D401871  
FEATURES  
• 128Kx36 or 256Kx18 Organizations.  
• 2.5V Core/1.5V Output Power Supply.  
• HSTL Input and HSTL Outputs.  
• Programmable Impedance Output Drivers.  
• Single Differential HSTL Clock.  
• Synchronous Pipeline Mode of Operation with Self-Timed  
Late Write.  
Cycle  
Time  
Access  
Time  
Organization  
Part Number  
K7D403671-H22  
K7D403671-H20  
K7D403671-H16  
K7D401871-H22  
K7D401871-H20  
K7D401871-H16  
44  
5
2.4  
2.7  
3.3  
2.4  
2.7  
3.3  
• Free Running Active High and Active Low Echo Clock Output  
Pin.  
• Asynchronous Output Enable.  
• Registered Addresses, Burst Control Inputs and Data Inputs.  
• Registered Outputs.  
• Single and Double Data Rate Burst Read and Write.  
• 4 Count Burst Operation  
128Kx36  
6
44  
5
256Kx18  
• JTAG 1149.1 Compatible Test Access port.  
• 153(9x17) Pin Ball Grid Array Package(14mm x 22mm).  
6
FUNCTIONAL BLOCK DIAGRAM  
SA[0:16]( or SA[0:17])  
Address  
Memory Array  
128Kx36  
or  
17(or 18)  
14(or 15)  
2:1  
Register  
Dec.  
MUX  
(Burst Address)  
CE  
(512Kx18)  
Clock  
Buffer  
Data Out  
K,K  
Data In  
Burst  
36(or 18)x2  
36(or 18)x2  
S/A Array  
Counter  
Comparator  
17(or 18)  
W/D  
Array  
Advance  
Control  
(Burst Write  
Address)  
B1  
B3  
Write  
Address  
SD/DD  
36(or 18)x2  
Register  
(2 stage)  
CE  
36(or 18)x2  
14(or 15)  
2 : 1 MUX  
Write Buffer  
Synchronous  
Select  
CE  
Strobe_out  
&
B2  
Echo Clock  
Output  
Output  
Buffer  
Data In  
Register  
(2 stage)  
R/W  
R/W control  
Data Output Strobe  
LD  
Data Output Enable  
State Machine  
Internal  
Clock  
36(or 18)  
DATA  
Generator  
XDIN  
KQ,KQ  
G
PIN DESCRIPTION  
Pin Name  
Pin Description  
Pin Name  
G
Pin Description  
K, K  
SA  
Differential Clocks  
Asynchronous Output Enable  
JTAG Test Clock  
Synchronous Address Input  
TCK  
TMS  
TDI  
SA0, SA1, SA2 Synchronous Burst Address Input  
JTAG Test Mode Select  
JTAG Test Data Input  
JTAG Test Data Output  
DQ  
VDD  
VDDQ  
VREF  
B1  
Synchronous Data I/O  
Core Power Supply  
TDO  
ZQ  
Output Power Supply  
Output Driver Impedance Control Input  
Linear Burst Order  
No Connect (Reserved)  
GND  
HSTL Input Reference Voltage  
Load External Address  
Burst R/W Enable  
LBO  
MODE  
VSS  
B2  
B3  
Single/Double Data Selection  
Differential Output Echo Clocks  
NC  
No Connection  
KQ, KQ  
Jan. 1999  
Rev 0.0  
- 1 -  

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