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K4T1G164QD PDF预览

K4T1G164QD

更新时间: 2024-02-19 20:22:05
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器双倍数据速率
页数 文件大小 规格书
27页 587K
描述
1Gb D-die DDR2 SDRAM Specification

K4T1G164QD 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:BGA, BGA92,9X21,32
Reach Compliance Code:compliant风险等级:5.84
访问模式:MULTI BANK PAGE BURST最长访问时间:0.6 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):200 MHz
I/O 类型:COMMON交错的突发长度:4,8
JESD-30 代码:R-PBGA-B92长度:21.7 mm
内存密度:1073741824 bit内存集成电路类型:DDR DRAM
内存宽度:16湿度敏感等级:3
功能数量:1端口数量:1
端子数量:92字数:67108864 words
字数代码:64000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:
组织:64MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA92,9X21,32封装形状:RECTANGULAR
封装形式:GRID ARRAY峰值回流温度(摄氏度):260
电源:1.8 V认证状态:Not Qualified
刷新周期:8192座面最大高度:1.2 mm
自我刷新:YES连续突发长度:4,8
子类别:DRAMs最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:11 mm

K4T1G164QD 数据手册

 浏览型号K4T1G164QD的Datasheet PDF文件第1页浏览型号K4T1G164QD的Datasheet PDF文件第2页浏览型号K4T1G164QD的Datasheet PDF文件第3页浏览型号K4T1G164QD的Datasheet PDF文件第5页浏览型号K4T1G164QD的Datasheet PDF文件第6页浏览型号K4T1G164QD的Datasheet PDF文件第7页 
K4T1G084QD  
K4T1G164QD  
DDR2 SDRAM  
1.0 Ordering Information  
Org.  
DDR2-800 5-5-5  
DDR2-800 6-6-6  
DDR2-667 5-5-5  
DDR2-533 4-4-4  
DDR2-400 3-3-3  
Package  
128Mx8 K4T1G084QD-ZC(L)E7 K4T1G084QD-ZC(L)F7 K4T1G084QD-ZC(L)E6 K4T1G084QD-ZC(L)D5 K4T1G084QD-ZC(L)CC 60 FBGA  
64Mx16 K4T1G164QD-ZC(L)E7 K4T1G164QD-ZC(L)F7 K4T1G164QD-ZC(L)E6 K4T1G164QD-ZC(L)D5 K4T1G164QD-ZC(L)CC 84 FBGA  
Note :  
1. Speed bin is in order of CL-tRCD-tRP.  
2. RoHS Compliant.  
2.0 Key Features  
Speed  
CAS Latency  
tRCD(min)  
tRP(min)  
DDR2-800 5-5-5  
DDR2-800 6-6-6  
DDR2-667 5-5-5  
DDR2-533 4-4-4  
DDR2-400 3-3-3  
Units  
tCK  
ns  
5
6
5
4
3
12.5  
12.5  
57.5  
15  
15  
60  
15  
15  
60  
15  
15  
60  
15  
15  
55  
ns  
tRC(min)  
ns  
• JEDEC standard 1.8V ± 0.1V Power Supply  
• VDDQ = 1.8V ± 0.1V  
• 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/  
pin, 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/  
sec/pin  
• 8 Banks  
• Posted CAS  
• Programmable CAS Latency: 3, 4, 5, 6  
• Programmable Additive Latency: 0, 1, 2, 3, 4, 5  
• Write Latency(WL) = Read Latency(RL) -1  
• Burst Length: 4 , 8(Interleave/nibble sequential)  
• Programmable Sequential / Interleave Burst Mode  
• Bi-directional Differential Data-Strobe (Single-ended data-  
strobe is an optional feature)  
• Off-Chip Driver(OCD) Impedance Adjustment  
• On Die Termination  
The 1Gb DDR2 SDRAM is organized as a 16Mbit x 8 I/Os x  
8banks or 8Mbit x 16 I/Os x 8 banks device. This synchronous  
device achieves high speed double-data-rate transfer rates of up  
to 800Mb/sec/pin (DDR2-800) for general applications.  
The chip is designed to comply with the following key DDR2  
SDRAM features such as posted CAS with additive latency, write  
latency = read latency - 1, Off-Chip Driver(OCD) impedance  
adjustment and On Die Termination.  
All of the control and address inputs are synchronized with a pair  
of externally supplied differential clocks. Inputs are latched at the  
crosspoint of differential clocks (CK rising and CK falling). All I/Os  
are synchronized with a pair of bidirectional strobes (DQS and  
DQS) in a source synchronous fashion. The address bus is used  
to convey row, column, and bank address information in a RAS/  
CAS multiplexing style. For example, 1Gb(x8) device receive 14/  
10/3 addressing.  
The 1Gb DDR2 device operates with a single 1.8V ± 0.1V power  
supply and 1.8V ± 0.1V VDDQ.  
The 1Gb DDR2 device is available in 60ball FBGAs(x8) and in  
84ball FBGAs(x16).  
• Special Function Support  
- PASR(Partial Array Self Refresh)  
- 50ohm ODT  
Note : The functionality described and the timing specifications included in  
this data sheet are for the DLL Enabled mode of operation.  
- High Temperature Self-Refresh rate enable  
• Average Refresh Period 7.8us at lower than TCASE 85°C,  
3.9us at 85°C < TCASE < 95 °C  
• All of Lead-free products are compliant for RoHS  
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “DDR2 SDRAM Device  
Operation & Timing Diagram”.  
2 of 29  
Rev. 1.0 March 2007  

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