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K4S561632D-NC600 PDF预览

K4S561632D-NC600

更新时间: 2024-02-07 19:55:49
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
9页 46K
描述
Synchronous DRAM, 16MX16, 5ns, CMOS, PDSO54, STSOP2-54

K4S561632D-NC600 技术参数

生命周期:Active包装说明:SOP,
Reach Compliance Code:compliantECCN代码:EAR99
风险等级:5.69访问模式:FOUR BANK PAGE BURST
最长访问时间:5 ns其他特性:AUTO/SELF REFRESH
JESD-30 代码:R-PDSO-G54内存密度:268435456 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:54字数:16777216 words
字数代码:16000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16MX16封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE自我刷新:YES
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子位置:DUAL
Base Number Matches:1

K4S561632D-NC600 数据手册

 浏览型号K4S561632D-NC600的Datasheet PDF文件第1页浏览型号K4S561632D-NC600的Datasheet PDF文件第2页浏览型号K4S561632D-NC600的Datasheet PDF文件第4页浏览型号K4S561632D-NC600的Datasheet PDF文件第5页浏览型号K4S561632D-NC600的Datasheet PDF文件第6页浏览型号K4S561632D-NC600的Datasheet PDF文件第7页 
K4S561632D  
CMOS SDRAM  
4M x 16Bit x 4 Banks Synchronous DRAM  
FEATURES  
GENERAL DESCRIPTION  
• JEDEC standard 3.3V power supply  
• LVTTL compatible with multiplexed address  
• Four banks operation  
The K4S561632D is 268,435,456 bits synchronous high data rate  
Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabri-  
cated with SAMSUNG's high performance CMOS technology. Syn-  
chronous design allows precise cycle control with the use of  
system clock I/O transactions are possible on every clock cycle.  
Range of operating frequencies, programmable burst length and  
programmable latencies allow the same device to be useful for a  
variety of high bandwidth, high performance memory system appli-  
cations.  
• MRS cycle with address key programs  
-. CAS latency (2 & 3)  
-. Burst length (1, 2, 4, 8 & Full page)  
-. Burst type (Sequential & Interleave)  
• All inputs are sampled at the positive going edge of the system  
clock.  
• Burst read single-bit write operation  
• DQM for masking  
ORDERING INFORMATION  
Part No.  
Max Freq.  
Interface Package  
• Auto & self refresh  
K4S561632D-NC/L60  
K4S561632D-NC/L7C  
K4S561632D-NC/L75  
K4S561632D-NC/L1H  
K4S561632D-NC/L1L  
166MHz(CL=3)  
133MHz(CL=2)  
133MHz(CL=3)  
100MHz(CL=2)  
100MHz(CL=3)  
• 64ms refresh period (8K Cycle)  
54pin  
LVTTL  
sTSOP(II)  
FUNCTIONAL BLOCK DIAGRAM  
LWE  
Data Input Register  
LDQM  
Bank Select  
4M x 16  
4M x 16  
4M x 16  
4M x 16  
DQi  
CLK  
ADD  
Column Decoder  
Latency & Burst Length  
LCKE  
Programming Register  
LWCBR  
LRAS  
LCBR  
LWE  
LCAS  
LDQM  
Timing Register  
CLK  
CKE  
CS  
RAS  
CAS  
WE  
L(U)DQM  
* Samsung Electronics reserves the right to change products or specification without notice.  
Rev. 0.1 Aug. 2002  

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