Datasheet > K4S561632C-TN60

K4S561632C-TN60

更新时间： 2023-06-15 00:00:00

品牌	Logo	应用领域
三星 - SAMSUNG		动态存储器光电二极管
页数	文件大小	规格书
11页	114K
描述
Synchronous DRAM, 16MX16, 5ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

K4S561632C-TN60 数据手册

K4S561632C

CMOS SDRAM

AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = -25 to 85°C)

Parameter

AC input levels (Vih/Vil)

Value

2.4/0.4

1.4

Unit

Input timing measurement reference level

Input rise and fall time

tr/tf = 1/1

1.4

Output timing measurement reference level

Output load condition

See Fig. 2

3.3V

Vtt = 1.4V

1200W

50W

VOH (DC) = 2.4V, IOH = -2mA

VOL (DC) = 0.4V, IOL = 2mA

Z0 = 50W

Output

50pF

870W

(Fig. 1) DC output load circuit

(Fig. 2) AC output load circuit

Notes :

1. The DC/AC Test Output Load of K4S561632C-TC(L)60 is 30pF.

2. The VDD condition of K4S561632C-TC(L)60 is 3.135V~3.6V.

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Version

Parameter

Symbol

Unit

Note

-60

-7C

-75

-1H

-1L

Row active to row active delay

RAS to CAS delay

tRRD(min)

tRCD(min)

tRP(min)

CLK

Row precharge time

tRAS(min)

tRAS(max

tRC(min)

tRDL(min)

tDAL(min)

Row active time

100

Row cycle time

2, 5

Last data in to row precharge

Last data in to Active delay

2 CLK + tRP

Last data in to new col. address delay

Last data in to burst stop

tCDL(min)

tBDL(min)

tCCD(min)

CLK

Col. address to col. address delay

CAS latency=3

CAS latency=2

Number of valid output

data

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.

SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.

Rev.0.1 Sept.2001

1...4 5 678 9 10 11

下载PDF

与K4S561632C-TN60相关器件

型号	品牌	描述	获取价格	数据表
K4S561632C-TN75	SAMSUNG	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54	获取价格
K4S561632C-TN7C	SAMSUNG	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54	获取价格
K4S561632C-TP75	SAMSUNG	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54	获取价格
K4S561632C-TP7C	SAMSUNG	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54	获取价格
K4S561632D	SAMSUNG	256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL	获取价格
K4S561632D-NC1H	SAMSUNG	Synchronous DRAM, 16MX16, 6ns, CMOS, PDSO54, 0.300 X 0.551 INCH, 0.50 MM PITCH, STSOP2-54	获取价格