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K4F660412B-TL50 PDF预览

K4F660412B-TL50

更新时间: 2024-11-12 10:05:59
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器光电二极管
页数 文件大小 规格书
20页 369K
描述
Fast Page DRAM, 16MX4, 50ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, TSOP2-32

K4F660412B-TL50 数据手册

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K4F660412B,K4F640412B  
CMOS DRAM  
16M x 4bit CMOS Dynamic RAM with Fast Page Mode  
DESCRIPTION  
This is a family of 16,777,216 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory  
cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power)  
are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities.  
Furthermore, Self-refresh operation is available in L-version. This 16Mx4 Fast Page Mode DRAM family is fabricated using Samsung¢s  
advanced CMOS process to realize high band-width, low power consumption and high reliability.  
FEATURES  
• Fast Page Mode operation  
• Part Identification  
- K4F660412B-JC/L(3.3V, 8K Ref., SOJ)  
- K4F640412B-JC/L(3.3V, 4K Ref., SOJ)  
- K4F660412B-TC/L(3.3V, 8K Ref., TSOP)  
- K4F640412B-TC/L(3.3V, 4K Ref., TSOP)  
• CAS-before-RAS refresh capability  
• RAS-only and Hidden refresh capability  
• Self-refresh capability (L-ver only)  
• Fast parallel test mode capability  
• LVTTL(3.3V) compatible inputs and outputs  
• Early Write or output enable controlled write  
• JEDEC Standard pinout  
Active Power Dissipation  
Unit : mW  
4K  
• Available in Plastic SOJ and TSOP(II) packages  
• +3.3V±0.3V power supply  
Speed  
-45  
8K  
360  
324  
288  
468  
432  
396  
-50  
-60  
Refresh Cycles  
Part  
NO.  
Refresh  
cycle  
Refresh time  
FUNCTIONAL BLOCK DIAGRAM  
Normal  
L-ver  
K4F660412B*  
K4F640412B  
8K  
4K  
RAS  
CAS  
W
64ms  
128ms  
Vcc  
Vss  
Control  
Clocks  
VBB Generator  
* Access mode & RAS only refresh mode  
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)  
CAS-before-RAS & Hidden refresh mode  
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)  
Row Decoder  
Refresh Timer  
Refresh Control  
Data in  
Buffer  
Memory Array  
16,777,216 x 4  
Cells  
DQ0  
to  
DQ3  
Refresh Counter  
Row Address Buffer  
Col. Address Buffer  
Performance Range  
Speed  
Data out  
Buffer  
tRAC  
45ns  
50ns  
60ns  
tCAC  
12ns  
13ns  
15ns  
tRC  
tPC  
A0~A12  
(A0~A11)*1  
OE  
-45  
-50  
-60  
80ns  
90ns  
110ns  
31ns  
35ns  
40ns  
A0~A10  
(A0~A11)*1  
Column Decoder  
Note) *1 : 4K Refresh  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to  
change products and specifications without notice.  

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