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K4E640811B-JC500 PDF预览

K4E640811B-JC500

更新时间: 2024-11-09 19:49:31
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
21页 415K
描述
EDO DRAM, 8MX8, 50ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32

K4E640811B-JC500 技术参数

生命周期:Obsolete零件包装代码:SOJ
包装说明:SOJ,针数:32
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.73
访问模式:FAST PAGE WITH EDO最长访问时间:50 ns
其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESHJESD-30 代码:R-PDSO-J32
长度:20.96 mm内存密度:67108864 bit
内存集成电路类型:EDO DRAM内存宽度:8
功能数量:1端口数量:1
端子数量:32字数:8388608 words
字数代码:8000000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8MX8封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装形状:RECTANGULAR
封装形式:SMALL OUTLINE认证状态:Not Qualified
座面最大高度:3.76 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
宽度:10.16 mmBase Number Matches:1

K4E640811B-JC500 数据手册

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K4E660811B,K4E640811B  
CMOS DRAM  
8M x 8bit CMOS Dynamic RAM with Extended Data Out  
DESCRIPTION  
This is a family of 8,388,608 x 8 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random  
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), package type (SOJ or  
TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capa-  
bilities. This 8Mx8 EDO Mode DRAM family is fabricated using Samsung¢s advanced CMOS process to realize high band-width, low  
power consumption and high reliability.  
FEATURES  
• Extended Data Out Mode operation  
• CAS-before-RAS refresh capability  
• RAS-only and Hidden refresh capability  
• Fast parallel test mode capability  
• TTL(5.0V) compatible inputs and outputs  
• Early Write or output enable controlled write  
• JEDEC Standard pinout  
• Part Identification  
- K4E660811B-JC(5.0V, 8K Ref., SOJ)  
- K4E640811B-JC(5.0V, 4K Ref., SOJ)  
- K4E660811B-TC(5.0V, 8K Ref., TSOP)  
- K4E640811B-TC(5.0V, 4K Ref., TSOP)  
Active Power Dissipation  
Unit : mW  
4K  
• Available in Plastic SOJ and TSOP(II) packages  
• +5.0V±10% power supply  
Speed  
-45  
8K  
550  
495  
440  
715  
660  
605  
-50  
-60  
Refresh Cycles  
FUNCTIONAL BLOCK DIAGRAM  
Part  
NO.  
Refresh  
cycle  
Refresh time  
Normal  
RAS  
CAS  
W
Vcc  
Vss  
K4E660811B*  
K4E640811B  
8K  
4K  
64ms  
Control  
Clocks  
VBB Generator  
* Access mode & RAS only refresh mode  
: 8K cycle/64ms  
CAS-before-RAS & Hidden refresh mode  
: 4K cycle/64ms  
Row Decoder  
Refresh Timer  
Refresh Control  
Data in  
Buffer  
Memory Array  
8,388,608 x 8  
Cells  
DQ0  
to  
DQ7  
Refresh Counter  
Row Address Buffer  
Col. Address Buffer  
Performance Range  
Speed  
Data out  
Buffer  
tRAC  
45ns  
50ns  
60ns  
tCAC  
12ns  
13ns  
15ns  
tRC  
tHPC  
17ns  
20ns  
25ns  
A0~A12  
(A0~A11)*1  
OE  
-45  
-50  
-60  
74ns  
84ns  
104ns  
A0~A9  
(A0~A10)*1  
Column Decoder  
Note) *1 : 4K Refresh  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to  
change products and specifications without notice.  

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