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JM38510/65803BEA PDF预览

JM38510/65803BEA

更新时间: 2024-11-24 11:25:15
品牌 Logo 应用领域
德州仪器 - TI 解码器驱动器解复用器逻辑集成电路
页数 文件大小 规格书
16页 533K
描述
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

JM38510/65803BEA 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP-16针数:16
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.46Is Samacsys:N
系列:HC/UH输入调节:STANDARD
JESD-30 代码:R-GDIP-T16长度:19.56 mm
负载电容(CL):50 pF逻辑集成电路类型:OTHER DECODER/DRIVER
最大I(ol):0.0052 A位数:4
功能数量:2端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:INVERTED封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED最大电源电流(ICC):0.08 mA
Prop。Delay @ Nom-Sup:44 ns传播延迟(tpd):255 ns
认证状态:Not Qualified筛选级别:MIL-M-38510 Class B
座面最大高度:5.08 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.92 mm
Base Number Matches:1

JM38510/65803BEA 数据手册

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ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢊ ꢃꢄ ꢅꢆ ꢇꢈ  
ꢋꢌꢍ ꢎ ꢏ ꢐꢎ ꢑꢁꢒ ꢓ ꢔ ꢃ ꢐꢎ ꢑꢁꢒ ꢋꢒꢅ ꢔꢋ ꢒꢕꢀ ꢖ ꢋꢒ ꢗꢌꢎꢓꢑ ꢘ ꢎꢒ ꢙꢒ ꢕ ꢀ  
SCLS108D − DECEMBER 1982 − REVISED SEPTEMBER 2003  
SN54HC139 . . . J OR W PACKAGE  
SN74HC139 . . . D, DB, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
Targeted Specifically for High-Speed  
Memory Decoders and Data-Transmission  
Systems  
D
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive Up To 10 LSTTL Loads  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1G  
1A  
1B  
1Y0  
1Y1  
1Y2  
1Y3  
GND  
V
CC  
2G  
2A  
2B  
2Y0  
2Y1  
2Y2  
2Y3  
Low Power Consumption, 80-µA Max I  
CC  
Typical t = 10 ns  
pd  
4-mA Output Drive at 5 V  
Low Input Current of 1 µA Max  
Incorporate Two Enable Inputs to Simplify  
Cascading and/or Data Reception  
SN54HC139 . . . FK PACKAGE  
(TOP VIEW)  
description/ordering information  
The ’HC139 devices are designed for  
high-performance  
memory-decoding  
or  
data-routing applications requiring very short  
propagation delay times. In high-performance  
memory systems, these decoders can minimize  
the effects of system decoding. When employed  
with high-speed memories utilizing a fast enable  
circuit, the delay time of these decoders and the  
enable time of the memory usually are less than  
the typical access time of the memory. This means  
that the effective system delay introduced by the  
decoders is negligible.  
3
2
1
20 19  
18  
2A  
2B  
NC  
1B  
1Y0  
NC  
4
5
6
7
8
17  
16  
15 2Y0  
14  
9 10 11 12 13  
1Y1  
1Y2  
2Y1  
NC − No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
PDIP − N  
PACKAGE  
Tube of 25  
Tube of 40  
SN74HC139N  
SN74HC139N  
SN74HC139D  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Tube of 90  
SN74HC139DR  
SN74HC139DT  
SN74HC139NSR  
SN74HC139DBR  
SN74HC139PW  
SN74HC139PWR  
SN74HC139PWT  
SNJ54HC139J  
SOIC − D  
HC139  
SOP − NS  
HC139  
HC139  
−40°C to 85°C  
SSOP − DB  
Reel of 2000  
Reel of 250  
Tube of 25  
TSSOP − PW  
HC139  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC139J  
SNJ54HC139W  
SNJ54HC139FK  
Tube of 150  
Tube of 55  
SNJ54HC139W  
SNJ54HC139FK  
−55°C to 125°C  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢔ ꢛ ꢦ ꢞ ꢝꢩ ꢤꢣ ꢡꢢ ꢣꢝ ꢟꢦ ꢨꢚ ꢠꢛ ꢡ ꢡꢝ ꢗꢑ ꢎꢐ ꢘꢕ ꢰ ꢐꢇꢱꢂ ꢇꢂꢉ ꢠꢨꢨ ꢦꢠ ꢞ ꢠ ꢟꢥ ꢡꢥꢞ ꢢ ꢠ ꢞ ꢥ ꢡꢥ ꢢꢡꢥ ꢩ  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
ꢤ ꢛꢨ ꢥꢢꢢ ꢝ ꢡꢫꢥ ꢞ ꢭꢚ ꢢꢥ ꢛ ꢝꢡꢥ ꢩꢪ ꢔ ꢛ ꢠꢨ ꢨ ꢝ ꢡꢫꢥ ꢞ ꢦꢞ ꢝ ꢩꢤꢣ ꢡꢢ ꢉ ꢦꢞ ꢝ ꢩꢤꢣ ꢡꢚꢝ ꢛ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

JM38510/65803BEA 替代型号

型号 品牌 替代类型 描述 数据表
SNJ54HC139J TI

完全替代

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SN54HC139J TI

完全替代

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

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