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JM38510/75603BSA PDF预览

JM38510/75603BSA

更新时间: 2024-11-01 20:59:35
品牌 Logo 应用领域
德州仪器 - TI 输出元件逻辑集成电路触发器
页数 文件大小 规格书
10页 224K
描述
AC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDFP20, CERAMIC, DFP-20

JM38510/75603BSA 技术参数

生命周期:Obsolete包装说明:DFP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84系列:AC
JESD-30 代码:R-GDFP-F20逻辑集成电路类型:D FLIP-FLOP
位数:8功能数量:1
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装形状:RECTANGULAR封装形式:FLATPACK
传播延迟(tpd):15 ns认证状态:Not Qualified
筛选级别:MIL-M-38510座面最大高度:2.286 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:6.731 mm最小 fmax:95 MHz
Base Number Matches:1

JM38510/75603BSA 数据手册

 浏览型号JM38510/75603BSA的Datasheet PDF文件第2页浏览型号JM38510/75603BSA的Datasheet PDF文件第3页浏览型号JM38510/75603BSA的Datasheet PDF文件第4页浏览型号JM38510/75603BSA的Datasheet PDF文件第5页浏览型号JM38510/75603BSA的Datasheet PDF文件第6页浏览型号JM38510/75603BSA的Datasheet PDF文件第7页 
February 1999  
54AC377 54ACT377  
Octal D Flip-Flop with Clock Enable  
n Ideal for addressable register applications  
n Clock enable for address and data synchronization  
applications  
n Eight edge-triggered D flip-flops  
n Buffered common clock  
General Description  
The ’AC/’ACT377 has eight edge-triggered, D-type flip-flops  
with individual D inputs and Q outputs. The common buff-  
ered Clock (CP) input loads all flip-flops simultaneously,  
when the Clock Enable (CE) is LOW.  
n Outputs source/sink 24 mA  
n See ’273 for master reset version  
n See ’373 for transparent latch version  
n See ’374 for TRI-STATE® version  
n ’ACT377 has TTL-compatible inputs  
n Standard Microcircuit Drawing (SMD)  
— ’AC377: 5962-88702  
The register is fully edge-triggered. The state of each D in-  
put, one setup time before the LOW-to-HIGH clock transi-  
tion, is transferred to the corresponding flip-flop’s Q output.  
The CE input must be stable only one setup time prior to the  
LOW-to-HIGH clock transition for predictable operation.  
Features  
n ICC reduced by 50%  
— ’ACT377: 5962-87697  
Logic Symbols  
IEEE/IEC  
DS100290-1  
DS100290-2  
Pin  
Description  
Names  
D0–D7  
CE  
Data Inputs  
Clock Enable (Active LOW)  
Data Outputs  
Q0–Q7  
CP  
Clock Pulse Input  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
FACT® is a registered trademark of Fairchild Semiconductor Corporation.  
© 1999 National Semiconductor Corporation  
DS100290  
www.national.com  

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