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JL82576EBSLAVZ PDF预览

JL82576EBSLAVZ

更新时间: 2024-02-20 08:10:09
品牌 Logo 应用领域
英特尔 - INTEL 通信时钟局域网外围集成电路
页数 文件大小 规格书
934页 7188K
描述
LAN Controller, CMOS, PBGA576, 25 X 25 MM, 1 MM PITCH, BGA-576

JL82576EBSLAVZ 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:BGA, BGA576,24X24,40
针数:576Reach Compliance Code:compliant
HTS代码:8542.31.00.01风险等级:5.75
地址总线宽度:边界扫描:NO
最大时钟频率:25 MHz通信协议:ASYNC, BIT; I2C
外部数据总线宽度:JESD-30 代码:S-PBGA-B576
长度:25 mm低功率模式:YES
端子数量:576最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA576,24X24,40
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):NOT SPECIFIED电源:1,1.8,3.3 V
认证状态:Not Qualified子类别:Serial IO/Communication Controllers
最大供电电压:1.89 V最小供电电压:1.71 V
标称供电电压:1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:25 mmuPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches:1

JL82576EBSLAVZ 数据手册

 浏览型号JL82576EBSLAVZ的Datasheet PDF文件第6页浏览型号JL82576EBSLAVZ的Datasheet PDF文件第7页浏览型号JL82576EBSLAVZ的Datasheet PDF文件第8页浏览型号JL82576EBSLAVZ的Datasheet PDF文件第10页浏览型号JL82576EBSLAVZ的Datasheet PDF文件第11页浏览型号JL82576EBSLAVZ的Datasheet PDF文件第12页 
Contents — Intel® 82576 GbE Controller  
2.1.9  
Testability Pins ................................................................................................................... 64  
2.1.10  
2.1.11  
2.2  
2.3  
2.4  
2.5  
2.6  
Reserved Pins and No-Connects ............................................................................................ 64  
Power Supply Pins............................................................................................................... 65  
Pull-ups/Pull-downs ................................................................................................................... 66  
Strapping ................................................................................................................................. 69  
Interface Diagram ..................................................................................................................... 70  
Pin List (Alphabetical) ................................................................................................................ 71  
Ball Out.................................................................................................................................... 73  
3.0  
Interconnects............................................................................................................................ 75  
3.1  
PCIe ........................................................................................................................................ 75  
3.1.1  
PCIe Overview .................................................................................................................... 75  
Architecture, Transaction and Link Layer Properties ........................................................... 76  
Physical Interface Properties........................................................................................... 77  
Advanced Extensions..................................................................................................... 77  
Functionality - General......................................................................................................... 77  
Native/Legacy .............................................................................................................. 77  
Locked Transactions...................................................................................................... 77  
End to End CRC (ECRC) ................................................................................................. 77  
Host I/F ............................................................................................................................. 77  
Tag IDs ....................................................................................................................... 77  
3.1.1.1  
3.1.1.2  
3.1.1.3  
3.1.2  
3.1.2.1  
3.1.2.2  
3.1.2.3  
3.1.3  
3.1.3.1  
3.1.3.1.1  
3.1.3.1.2  
TAG ID Allocation for Read Transactions........................................................................ 77  
TAG ID Allocation for Write Transactions ....................................................................... 78  
Case 1 - DCA Disabled in the System:.................................................................... 78  
Case 2 - DCA Enabled in the System, but Disabled for the Request: ........................... 79  
Case 3 - DCA Enabled in the System, DCA Enabled for the Request:........................... 79  
3.1.3.1.2.1  
3.1.3.1.2.2  
3.1.3.1.2.3  
3.1.3.2  
3.1.3.2.1  
3.1.3.2.2  
3.1.3.2.3  
Completion Timeout Mechanism...................................................................................... 79  
Completion Timeout Enable......................................................................................... 80  
Resend Request Enable............................................................................................... 80  
Completion Timeout Period.......................................................................................... 80  
3.1.4  
3.1.4.1  
3.1.4.1.1  
3.1.4.1.2  
3.1.4.2  
3.1.4.2.1  
3.1.4.2.2  
3.1.4.3  
3.1.4.3.1  
3.1.4.3.2  
3.1.4.4  
3.1.4.4.1  
3.1.4.5  
Transaction Layer................................................................................................................ 81  
Transaction Types Accepted by the 82576........................................................................ 82  
Configuration Request Retry Status.............................................................................. 82  
Partial Memory Read and Write Requests ...................................................................... 82  
Transaction Types Initiated by the 82576......................................................................... 83  
Data Alignment.......................................................................................................... 83  
Multiple Tx Data Read Requests................................................................................... 83  
Messages..................................................................................................................... 84  
Message Handling by the 82576 (as a Receiver)............................................................. 84  
Message Handling by the 82576 (as a Transmitter) ........................................................ 84  
Ordering Rules ............................................................................................................. 85  
Out of Order Completion Handling................................................................................ 85  
Transaction Definition and Attributes ............................................................................... 86  
Max Payload Size....................................................................................................... 86  
Traffic Class (TC) and Virtual Channels (VC) .................................................................. 86  
Relaxed Ordering....................................................................................................... 86  
Snoop Not Required ................................................................................................... 86  
No Snoop and Relaxed Ordering for LAN Traffic.............................................................. 86  
3.1.4.5.1  
3.1.4.5.2  
3.1.4.5.3  
3.1.4.5.4  
3.1.4.5.5  
3.1.4.5.5.1  
3.1.4.5.5.2  
No-Snoop Option for Payload ................................................................................ 87  
No Snoop Option for TSO Header........................................................................... 87  
3.1.4.6  
3.1.4.6.1  
3.1.4.6.2  
3.1.4.6.3  
3.1.4.6.4  
Flow Control................................................................................................................. 87  
82576 Flow Control Rules............................................................................................ 87  
Upstream Flow Control Tracking................................................................................... 88  
Flow Control Update Frequency.................................................................................... 88  
Flow Control Timeout Mechanism ................................................................................. 88  
Error Forwarding........................................................................................................... 89  
3.1.4.7  
3.1.5  
3.1.5.1  
3.1.5.2  
3.1.5.3  
Data Link Layer................................................................................................................... 89  
ACK/NAK Scheme ......................................................................................................... 89  
Supported DLLPs .......................................................................................................... 89  
Transmit EDB Nullifying ................................................................................................. 90  
Physical Layer..................................................................................................................... 90  
3.1.6  
320961-015EN  
Revision: 2.61  
December 2010  
Intel® 82576 GbE Controller  
Datasheet  
9

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