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JL82576EBSLAVZ PDF预览

JL82576EBSLAVZ

更新时间： 2024-01-02 16:55:43
品牌 Logo 应用领域
英特尔 - INTEL 通信时钟局域网外围集成电路
页数 文件大小 规格书
934页 7188K
描述
LAN Controller, CMOS, PBGA576, 25 X 25 MM, 1 MM PITCH, BGA-576

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JL82576EBSLAVZ 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：BGA, BGA576,24X24,40
针数：576Reach Compliance Code：compliant
HTS代码：8542.31.00.01风险等级：5.75
地址总线宽度：边界扫描：NO
最大时钟频率：25 MHz通信协议：ASYNC, BIT; I2C
外部数据总线宽度：JESD-30 代码：S-PBGA-B576
长度：25 mm低功率模式：YES
端子数量：576最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA576,24X24,40
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：NOT SPECIFIED电源：1,1.8,3.3 V
认证状态：Not Qualified子类别：Serial IO/Communication Controllers
最大供电电压：1.89 V最小供电电压：1.71 V
标称供电电压：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：25 mmuPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches：1

JL82576EBSLAVZ 数据手册

 浏览型号JL82576EBSLAVZ的Datasheet PDF文件第928页浏览型号JL82576EBSLAVZ的Datasheet PDF文件第929页浏览型号JL82576EBSLAVZ的Datasheet PDF文件第930页浏览型号JL82576EBSLAVZ的Datasheet PDF文件第931页浏览型号JL82576EBSLAVZ的Datasheet PDF文件第932页浏览型号JL82576EBSLAVZ的Datasheet PDF文件第933页 
Intel® 82576 GbE Controller — Changes from the 82575  
Table A-1.  
Changes in Programming Interface Relative to 82575  
Feature  
Registers  
Description  
Impact on Legacy Drivers  
Receive  
Filtering  
FFMT, FFVT,  
FFLT, TFFLT,  
FTFT,  
Registers replaced with FHFT & FTFT using the  
82598’s filters layout.  
Wakeup flex filter programming  
needs to be updated  
RCTL  
Removed Receive Descriptor Minimum Threshold  
Size field - replaced by per queue SRRCTL.RDMTS  
fields. Default values are the same.  
None assuming default values are  
kept.  
RAH  
Changed the queue indication from queue number  
to pools bitmap.  
Drivers supporting VMDQ1.0 should  
change programming of RAH.  
VMD_CTL  
Default Queue is now shared between the pools  
instead of default queue per pool,  
Drivers supporting VMDQ1.0 should  
change programming of VMD_CTL.  
MRQC  
RETA  
Added encoding for the Multiple Receive Queues  
Enable field. Fields supported in 82575 are kept.  
None  
Moved the queue index to bits 3:0 of each entry.  
No support for individual tables for each pool.  
Drivers supporting RSS should update  
table programming.  
VFQA0,1  
TXDCTL  
Replaced by VLVF registers  
Use new registers for VLAN queueing  
Transmit  
Priority bit removed, as a new arbitration scheme  
has been added to the 82576.  
Driver using per Tx queue priority  
should update to new arbiter.  
Threshold fields are 5 bits instead of 6 due to the  
reduction in descriptor cache size.  
do not program threshold bigger than  
cache size.  
TXCTL  
CPUid field expanded to 8 bits to support new DCA  
standard  
Drivers supporting DCA should  
update to new register layout.  
Tx Queues  
registers  
Moved to a different address space. Aliases for Q1-  
3 at 82575 address space.  
None  
Tx contexts  
The 82576 allows 2 contexts per queue instead of  
16 global contexts supported in 82575  
Change context indexing.  
Limitation on header buffers layout.  
Use new SerDes mode  
TSO  
interleaving  
TSO flows may now be interleaved at the L2 level.  
Legacy SerDes mode removed - Register removed.  
Legacy  
Serdes  
Registers  
TXCW, RXCW,  
SEC  
New  
PCS_LCTL  
CRCERRS  
Added possibility of HW based resolving of the flow  
control auto negotiation. Controlled by the  
PCS_LCTL.Force Flow control bit  
Either use HW based AN resolving or  
set this bit and use legacy SW based  
resolving.  
SerDes  
Statistics  
Doesn’t count alignment errors anymore. Counts  
RX errors. This register is now equivalent to the  
frameCheckError counter as defined by IEEE  
802.3.  
Change MIB & OID calculation.  
Flow  
control  
FCAL, FCAH  
Registers are read only  
None.  
§ §  
Intel® 82576 GbE Controller  
Datasheet  
934  
320961-015EN  
Revision: 2.61  
December 2010  
1...931932933934

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