Datasheet > ISPLSI2128VE135LT100

ISPLSI2128VE135LT100

更新时间： 2024-10-29 04:15:47

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
20页	200K
描述
3.3V In-System Programmable SuperFAST⑩ High Density PLD

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

ISPLSI2128VE135LT100 数据手册

浏览型号ISPLSI2128VE135LT100的Datasheet PDF文件第2页

浏览型号ISPLSI2128VE135LT100的Datasheet PDF文件第3页

浏览型号ISPLSI2128VE135LT100的Datasheet PDF文件第4页

浏览型号ISPLSI2128VE135LT100的Datasheet PDF文件第5页

浏览型号ISPLSI2128VE135LT100的Datasheet PDF文件第6页

浏览型号ISPLSI2128VE135LT100的Datasheet PDF文件第7页

Lead-

ispLSI 2128VE

Packag

Options

ailable!

3.3V In-System Programmable

SuperFAST™ High Density PLD

Features

Functional Block Diagram*

• SuperFAST HIGH DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC

— 6000 PLD Gates

Output Routing Pool (ORP)

D7 D6

Output Routing Pool (ORP)

— 128 and 64 I/O Pin Versions, Eight Dedicated Inputs

— 128 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— 100% Functional, JEDEC and Pinout Compatible

with ispLSI 2128V Devices

Logic

Array

GLB

• 3.3V LOW VOLTAGE 2128 ARCHITECTURE

— Interfaces with Standard 5V TTL Devices

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 250MHz Maximum Operating Frequency

— tpd = 4.0ns Propagation Delay

Global Routing Pool (GRP)

— Electrically Erasable and Reprogrammable

— Non-Volatile

Output Routing Pool (ORP)

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

0139A/2128VE

*128 I/O Version Shown

• IN-SYSTEM PROGRAMMABLE

— 3.3V In-System Programmability (ISP™) Using

Boundary Scan Test Access Port (TAP)

Description

The ispLSI 2128VE is a High Density Programmable

Logic Device available in 128 and 64 I/O-pin versions.

The device contains 128 Registers, eight Dedicated

Input pins, three Dedicated Clock Input pins, two dedi-

cated Global OE input pins and a Global Routing Pool

(GRP). The GRP provides complete interconnectivity

between all of these elements. The ispLSI 2128VE

features in-system programmability through the Bound-

ary Scan Test Access Port (TAP) and is 100% IEEE

1149.1 Boundary Scan Testable. The ispLSI 2128VE

offers non-volatile reprogrammability of the logic, as well

as the interconnect to provide truly reconfigurable sys-

tems.

— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of Wired-

OR Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

The basic unit of logic on the ispLSI 2128VE device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. D7 (see Figure 1). There are a total of 32 GLBs in the

ispLSI 2128VE device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/ExclusiveORarray, andfouroutputswhichcan

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

• LEAD-FREE PACKAGE OPTIONS

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

August 2004

2128ve_12

12 3 4 5 6 7...20

中文翻译

下载PDF

与ISPLSI2128VE135LT100相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI2128VE-135LT100	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VE135LT100I	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VE-135LT100I	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VE135LT176	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VE-135LT176	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VE135LT176I	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VE-135LT176I	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VE135LTN100	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D
ISPLSI2128VE-135LTN100	LATTICE	获取价格	3.3V In-System Programmable SuperFASTâ¢ High
ISPLSI2128VE135LTN100I	LATTICE	获取价格	3.3V In-System Programmable SuperFAST⑩ High D

与ISPLSI2128VE135LT100相关文章

三星深化印度制造布局，供应链本地化进程加速
2024-10-29

15
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

17
纳微科技震撼发布GaNSlim革新氮化镓功率芯片
2024-10-18

41
意法半导体发布第四代SiC技术，助力电动汽车电驱
2024-10-15

49

产品中心

服务支持

精选活动

关于我们

帮助中心

ISPLSI2128VE135LT100

ISPLSI2128VE135LT100 数据手册

与ISPLSI2128VE135LT100相关器件

与ISPLSI2128VE135LT100相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

ISPLSI2128VE135LT100

ISPLSI2128VE135LT100 数据手册

与ISPLSI2128VE135LT100相关器件

与ISPLSI2128VE135LT100相关文章

您还可以找

您在本页遇到什么问题？