Datasheet > IS93C56A-3GRLI

IS93C56A-3GRLI

更新时间： 2024-02-20 18:21:41

品牌	Logo	应用领域
美国芯成 - ISSI		可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数	文件大小	规格书
13页	61K
描述
EEPROM, 128X16, Serial, CMOS, PDSO8, LEAD FREE, SOIC-8

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技术参数
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IS93C56A-3GRLI 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP, SOP8,.25	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.51	风险等级：	5.41
备用内存宽度：	8	最大时钟频率 (fCLK)：	2 MHz
数据保留时间-最小值：	40	耐久性：	1000000 Write/Erase Cycles
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e3
内存密度：	2048 bit	内存集成电路类型：	EEPROM
内存宽度：	16	湿度敏感等级：	3
功能数量：	1	端子数量：	8
字数：	128 words	字数代码：	128
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	128X16
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	并行/串行：	SERIAL
峰值回流温度（摄氏度）：	260	电源：	3/5 V
认证状态：	Not Qualified	串行总线类型：	MICROWIRE
最大待机电流：	0.000002 A	子类别：	EEPROMs
最大压摆率：	0.002 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	2.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
最长写入周期时间 (tWC)：	5 ms	写保护：	SOFTWARE
Base Number Matches：	1

IS93C56A-3GRLI 数据手册

IS93C56A

IS93C66A

ISSI

Write Enable (WEN)

Write All (WRALL)

The write enable (WEN) instruction must be executed

before any device programming (WRITE, WRALL,

ERASE, and ERAL) can be done. When Vcc is applied,

this device powers up in the write disabled state. The

devicethenremainsinawritedisabledstateuntilaWEN

instruction is executed. Thereafter, the device remains

enabled until a WDS instruction is executed or until Vcc

is removed. (See Figure 4.) (Note: Chip select must

remain LOW until Vcc reaches its operational value.)

The write all (WRALL) instruction programs all registers

withthedatapatternspecifiedintheinstruction.Aswiththe

WRITE instruction, the falling edge of CS must occur to

initiate the self-timed programming cycle. If CS is then

broughtHIGHafteraminimumwaitof200ns(tCS),theDOUT

pin indicates the READY/BUSY status of the chip (see

Figure 6). Vcc is required to be above 4.5V for WRALL to

function properly.

Write Disable (WDS)

Write (WRITE)

The write disable (WDS) instruction disables all programming

capabilities. This protects the entire device against acci-

dental modification of data until a WEN instruction is

executed. (When Vcc is applied, this part powers up in the

write disabled state.) To protect data, a WDS instruction

should be executed upon completion of each programming

operation.

TheWRITEinstructionincludes8or16bitsofdatatobe

written into the specified register. After the last data bit

has been applied to DIN, and before the next rising edge

of SK, CS must be brought LOW. If the device is write-

enabled, then the falling edge of CS initiates the self-

timed programming cycle (see WEN).

IfCSisbroughtHIGH,afteraminimumwaitof200ns(5V

operation) after the falling edge of CS (t^CS) DOUT will

indicatetheREADY/BUSYstatusofthechip.Logical“0”

meansprogrammingisstillinprogress;logical“1”means

the selected register has been written, and the part is

readyforanotherinstruction(seeFigure5).TheREADY/

BUSYstatuswillnotbeavailableif:a)TheCSinputgoes

HIGHaftertheendoftheself-timedprogrammingcycle,

tWP; or b) Simultaneously CS is HIGH, Din is HIGH, and

SK goes HIGH, which clears the status flag.

Erase Register (ERASE)

After the erase instruction is entered, CS must be brought

LOW.ThefallingedgeofCSinitiatestheself-timedinternal

programming cycle. Bringing CS HIGH after a minimum of

tCS, will cause DOUT to indicate the READ/BUSY status of the

chip:alogical“0”indicatesprogrammingisstillinprogress;

a logical “1” indicates the erase cycle is complete and the

part is ready for another instruction (see Figure 8).

Erase All (ERAL)

Fullchiperaseisprovidedforeaseofprogramming.Erasing

the entire chip involves setting all bits in the entire memory

array to a logical “1” (see Figure 9). Vcc is required to be

above 4.5V for ERALL to function properly.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. 00E

06/21/05

1 234 5 6 7...13

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与IS93C56A-3GRLI相关器件

型号	品牌	描述	获取价格	数据表
IS93C56A-3P	ISSI	暂无描述	获取价格
IS93C56A-3PA	ETC	EEPROM	获取价格
IS93C56A-3PI	ISSI	2K-BIT/4K-BIT SERIAL ELECTRICALLY ERASABLE PROM	获取价格
IS93C56A-3PLA3	ISSI	2K-BIT/4K-BIT SERIAL ELECTRICALLY ERASABLE PROM	获取价格
IS93C56A-3PLI	ISSI	EEPROM, 128X16, Serial, CMOS, PDIP8, 0.300 INCH, LEAD FREE, PLASTIC, DIP-8	获取价格
IS93C56A-3ZI	ETC	EEPROM	获取价格

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