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IS82C600-10BI PDF预览

IS82C600-10BI

更新时间: 2024-11-18 14:38:07
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
21页 128K
描述
Standard SRAM, 64KX16, 10ns, CMOS, PBGA119, PLASTIC, BGA-119

IS82C600-10BI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:PLASTIC, BGA-119针数:119
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.92
最长访问时间:10 nsI/O 类型:COMMON
JESD-30 代码:R-PBGA-B119JESD-609代码:e0
长度:22 mm内存密度:1048576 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端口数量:2端子数量:119
字数:65536 words字数代码:64000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:64KX16
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA119,7X17,50封装形状:RECTANGULAR
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not Qualified座面最大高度:2.41 mm
子类别:SRAMs最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

IS82C600-10BI 数据手册

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®
IS82C600  
TRAILBLAZER  
High-Speed SRAM with  
PRELIMINARY  
JANUARY 1999  
ISSI  
Address Decoding and Ready Logic  
FEATURES  
• Features Address Decoding and Ready Logic  
— A total of six Chip Selects  
• Zero wait-state performance on the Primary  
Bus  
— Point-to-point interface between the SRAM  
and the high-speed processor  
— Supports “Ready” logic signal generation for  
memory and I/O  
• Seamless interface to Texas Instruments’  
TMS320LC54x high-speed processor  
— Eliminates PALs for address decoding and  
ready logic  
• Integrates the single-ported SRAM with a dual-  
ported interface and handshake  
— No “glue logic” interface for local peripherals  
on the Secondary Bus processor  
— 9 ns access time to the SRAM  
• Allows dynamic re-allocation of memory spaces  
for transparent block moves  
— Can also be used as a standalone, high-  
speed SRAM  
— Programmable memory decoding allows  
memory blocks to be accessed as either  
Program Space (PS) or Data Space (DS)  
• Integrates the port-to-port bridge function  
— Broadcasts all processor cycles from  
Primary Bus to the Secondary Bus  
— Programmable registers to map the internal  
SRAM memory and external secondary port  
devices into Data Space (DS), Program  
Space (PS) and I/O Space (IS)  
— Programmability to only broadcast  
non-SRAM cycles to the Secondary Bus  
— Supports older, slower peripheral devices on  
the Secondary Bus  
• Can also be used as a standalone, high-speed  
SRAM  
— Allows the processor transparent access to  
the devices on the Secondary Bus through  
XCVR pin  
• Allows the shadowing of the ROM on the  
Secondary Bus into the on-board SRAM  
— Supports a Boot ROM on the Secondary Bus  
GENERAL DESCRIPTION  
point, low-load interconnect to the high-speed memory  
andbufferingoftheslowerspeeddevices.Thiscouldallow  
the processors to operate at a maximum frequency with  
zero wait-states. Also, it eases PCB timing and layout-  
related considerations, often allowing a reduction in the  
number of PC board layers and the lowering of noise.  
Programmable decodes and "Ready" generation logic  
built into the TrailBlazer eliminates the need for expensive  
PALs, other glue logic, and additional board space.  
The IS82C600 TrailBlazer simplifies high-speed system  
designandlayout, providinganSRAMwithzerowait-state  
performance up to 90 MHz, address coding, and “Ready”  
logic. In many cases, TrailBlazer allows existing system  
designs to be easily upgraded, enabling the re-use of  
already available ASICs and glue logic.  
AkeybenefitoftheTrailBlazerdeviceisitsabilitytorelieve  
high-performance processors from a necessity to drive  
heavily loaded multidrop buses by providing a point-to-  
This document contains PRELIMINARY DATA. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product.  
We assume no responsibility for any errors which may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
PRELIMINARY TB001-0B  
1
01/20/99  

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