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IS82C50A-5

更新时间： 2024-11-17 22:48:03
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英特矽尔 - INTERSIL 外围集成电路数据传输通信时钟
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21页 103K
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CMOS Asynchronous Communications Element

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IS82C50A-5 数据手册

 浏览型号IS82C50A-5的Datasheet PDF文件第2页浏览型号IS82C50A-5的Datasheet PDF文件第3页浏览型号IS82C50A-5的Datasheet PDF文件第4页浏览型号IS82C50A-5的Datasheet PDF文件第5页浏览型号IS82C50A-5的Datasheet PDF文件第6页浏览型号IS82C50A-5的Datasheet PDF文件第7页 
82C50A  
CMOS Asynchronous  
Communications Element  
March 1997  
Features  
Description  
• Single Chip UART/BRG  
The 82C50A Asynchronous Communication Element (ACE)  
is a high performance programmable Universal Asynchro-  
nous Receiver/Transmitter (UART) and Baud Rate Genera-  
tor (BRG) on a single chip. Using Intersil’s advanced Scaled  
SAJI IV CMOS Process, the ACE will support data rates  
from DC to 625K baud (0-10MHz clock).  
• DC to 625K Baud (DC to 10MHz Clock)  
• Crystal or External Clock Input  
• On Chip Baud Rate Generator 1 to 65535 Divisor  
Generates 16X Clock  
• Prioritized Interrupt Mode  
• Fully TTL/CMOS Compatible  
• Microprocessor Bus Oriented Interface  
• 80C86/80C88 Compatible  
• Scaled SAJI IV CMOS Process  
• Low Power - 1mA/MHz Typical  
• Modem Interface  
• Line Break Generation and Detection  
• Loopback and Echo Modes  
• Doubled Buffered Transmitter and Receiver  
• Single 5V Supply  
The ACE’s receiver circuitry converts start, data, stop, and  
parity bits into a parallel data word. The transmitter circuitry  
converts a parallel data word into serial form and appends  
the start, parity, and stop bits. The word length is program-  
mable to 5, 6, 7, or 8 data bits. Stop bit selection provides a  
choice of 1,1.5, or 2 stop bits.  
The Baud Rate Generator divides the clock by a divisor  
16  
programmable from 1 to 2 -1 to provide standard RS-232C  
baud rates when using any one of three industry standard  
baud rate crystals (1.8432MHz, 2.4576MHz, or 3.072MHz).  
A programmable buffered clock output (BAUDOUT) provides  
either a buffered oscillator or 16X (16 times the data rate)  
baud rate clock for general purpose system use.  
Ordering Information  
TEMPERATURE  
PKG.  
o
PACKAGE  
RANGE ( C)  
625K BAUD  
CP82C50A-5  
IP82C50A-5  
CS82C50A-5  
IS82C50A-5  
CD82C50A-5  
ID82C50A-5  
MD82C50A-5/B  
NO.  
E40.6  
E40.6  
N44.65  
N44.65  
F40.6  
F40.6  
F40.6  
PDIP  
0 to +70  
-40 to +85  
0 to +70  
To meet the system requirements of a CPU interfacing to an  
asynchronous channel, the modem control signals RTS,  
CTS, DSR, DTR, RI, DCD are provided. Inputs and outputs  
have been designed with full TTL/CMOS compatibility in  
order to facilitate mixed TTL/NMOS/CMOS system design.  
PLCC  
-40 to +85  
0 to +70  
CERDIP  
-40 to +85  
-55 to +125  
Functional Diagram  
MICROPROCESSOR INTERFACE  
CSO  
CS1  
CS2  
12  
13  
14  
24 CSOUT  
23  
DDIS  
INTERRUPT  
ENABLE,  
ID, & CONTROL  
30 INTRPT  
ADS  
25  
A0  
A1  
A2  
MR  
28  
27  
26  
35  
UART  
10  
9
SIN  
RECEIVER  
RCLK  
15 BAUDOUT  
DISTR 22  
DISTR 21  
DIVISOR LATCH  
AND BAUD RATE  
GENERATOR  
LINE STATUS  
AND CONTROL  
16  
17  
XTAL1  
XTAL2  
DOSTR 19  
DOSTR 18  
11  
32  
33  
34  
SOUT  
RTS  
TRANSMITTER  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
1
2
3
4
5
6
7
MODEM  
DTR  
OUT1  
MODEM CONTROL  
MODEM STATUS  
31  
36  
37  
38  
39  
OUT2  
CTS  
DSR  
DCD  
RI  
D7  
8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 2958.1  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
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IS82C50A-5 替代型号

型号 品牌 替代类型 描述 数据表
CS82C50A-596 INTERSIL

完全替代

 CMOS Asynchronous
IS82C50A-5Z INTERSIL

类似代替

 CMOS Asynchronous
CP82C50A-5Z INTERSIL

功能相似

 CMOS Asynchronous

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