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CP82C50A-5Z

更新时间: 2024-11-18 03:26:23
品牌 Logo 应用领域
英特矽尔 - INTERSIL 外围集成电路光电二极管数据传输通信时钟
页数 文件大小 规格书
25页 283K
描述
CMOS Asynchronous

CP82C50A-5Z 数据手册

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82C50A  
®
Data Sheet  
August 24, 2006  
FN2958.5  
CMOS Asynchronous  
Features  
The 82C50A Asynchronous Communication Element  
(ACE) is a high performance programmable Universal  
Asynchronous Receiver/Transmitter (UART) and Baud  
Rate Generator (BRG) on a single chip. Using Intersil’s  
advanced Scaled SAJI IV CMOS Process, the ACE will  
support data rates from DC to 625K baud (0-10MHz clock).  
• Single Chip UART/BRG  
• DC to 625K Baud (DC to 10MHz Clock)  
• Crystal or External Clock Input  
• On Chip Baud Rate Generator 1 to 65535 Divisor  
Generates 16X Clock  
The ACE’s receiver circuitry converts start, data, stop, and  
parity bits into a parallel data word. The transmitter circuitry  
converts a parallel data word into serial form and appends  
the start, parity, and stop bits. The word length is  
programmable to 5, 6, 7, or 8 data bits. Stop bit selection  
provides a choice of 1,1.5, or 2 stop bits.  
• Prioritized Interrupt Mode  
• Fully TTL/CMOS Compatible  
• Microprocessor Bus Oriented Interface  
• 80C86/80C88 Compatible  
• Scaled SAJI IV CMOS Process  
• Low Power - 1mA/MHz Typical  
• Modem Interface  
The Baud Rate Generator divides the clock by a divisor  
16  
programmable from 1 to 2 -1 to provide standard RS-  
232C baud rates when using any one of three industry  
standard baud rate crystals (1.8432MHz, 2.4576MHz, or  
3.072MHz). A programmable buffered clock output  
(BAUDOUT) provides either a buffered oscillator or 16X (16  
times the data rate) baud rate clock for general purpose  
system use.  
• Line Break Generation and Detection  
• Loopback and Echo Modes  
• Doubled Buffered Transmitter and Receiver  
• Single 5V Supply  
To meet the system requirements of a CPU interfacing to  
an asynchronous channel, the modem control signals RTS,  
CTS, DSR, DTR, RI, DCD are provided. Inputs and outputs  
have been designed with full TTL/CMOS compatibility in  
order to facilitate mixed TTL/NMOS/CMOS system design.  
• Pb-Free Plus Anneal Available (RoHS Compliant)  
Ordering Information  
TEMP  
PART  
MARKING  
RANGE  
(°C)  
PKG.  
625K BAUD  
PACKAGE DWG. #  
CP82C50A-5  
CP82C50A-5  
0 to +70 40 Ld PDIP E40.6  
CP82C50A-5Z  
(Note)  
CP82C50A-5Z 0 to +70 40 Ld PDIP E40.6  
(Pb-free)  
CS82C50A-596 CS82C50A-5  
0 to +70 44 Ld PLCC N44.65  
Tape and  
Reel  
CS82C50A-5Z  
(Note)  
CS82C50A-5Z 0 to +70 44 Ld PLCC N44.65  
(Pb-free)  
CS82C50A-5Z96 CS82C50A-5Z 0 to +70 44 Ld PLCC N44.65  
(Note)  
Tape and  
Reel  
(Pb-free)  
IS82C50A-5  
IS82C50A-5  
-40 to +85 44 Ld PLCC N44.65  
IS82C50A-5Z  
(Note)  
IS82C50A-5Z -40 to +85 44 Ld PLCC N44.65  
(Pb-free)  
NOTE: Intersil Pb-free plus anneal products employ special Pb-free  
material sets; molding compounds/die attach materials and 100% matte  
tin plate termination finish, which are RoHS compliant and compatible  
with both SnPb and Pb-free soldering operations. Intersil Pb-free  
products are MSL classified at Pb-free peak reflow temperatures that  
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1
1-888-INTERSIL or1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright © Intersil Americas Inc. 2003, 2005, 2006. All Rights Reserved  
All other trademarks mentioned are the property of their respective owners.  

CP82C50A-5Z 替代型号

型号 品牌 替代类型 描述 数据表
CS82C50A-5Z INTERSIL

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CS82C50A-5Z96 INTERSIL

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