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IS61VPS102436A-166TQL-TR

更新时间： 2024-11-27 13:08:55

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IS61VPS102436A IS61LPS102436A

IS61VPS204818A IS61LPS204818A

1Mb x 36, 2Mb x 18

36Mb SYNCHRONOUS PIPELINED,

SINGLE CYCLE DESELECT STATIC RAM

MARCH 2008

DESCRIPTION

FEATURES

The ISSI IS61LPS/VPS102436A and IS61LPS/VPS

204818A are high-speed, low-power synchronous static

RAMsdesignedtoprovideburstable,high-performancememory

for communication and networking applications. The

IS61LPS/VPS102436Aisorganizedas1,048,476words

by 36 bits. The IS61LPS/VPS204818A is organized as

2M-word by 18 bits. Fabricated with ISSI's advanced

CMOS technology, the device integrates a 2-bit burst

counter,high-speedSRAMcore,andhigh-drivecapability

outputs into a single monolithic circuit. All synchronous

inputs pass through registers controlled by a positive-

edge-triggeredsingleclockinput.

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth

expansion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

Write cycles are internally self-timed and are initiated by

therisingedgeoftheclockinput. Writecyclescanbeone

tofourbyteswideascontrolledbythewritecontrolinputs.

• Snooze MODE for reduced-power standby

• Power Supply

Separatebyteenablesallowindividualbytestobewritten.

The byte write operation is performed by using the byte

write enable (BWE) input combined with one or more

individual byte write signals (BWx). In addition, Global

Write (GW) is available for writing all bytes at one time,

regardless of the byte write controls.

LPS: V^DD3.3V + 5%, VDDQ 3.3V/2.5V + 5%

VPS: V^DD2.5V + 5%, VDDQ 2.5V + 5%

• JEDEC 100-Pin TQFP and 165-ball PBGA

packages

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

inputpins.Subsequentburstaddressescanbegenerated

internally and controlled by the ADV (burst address

advance) input pin.

• Lead-free available

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH or

left floating.

FAST ACCESS TIME

Symbol

tKQ

Parameter

200

3.1

166

3.5

Units

Clock Access Time

Cycle Time

tKC

Frequency

200

166

MHz

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany

publishedinformationandbeforeplacingordersforproducts.

Integrated Silicon Solution, Inc.

Rev. B

03/27/08

12 3 4 5 6 7...21

中文翻译

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与IS61VPS102436A-166TQL-TR相关器件

型号	品牌	获取价格	描述	数据表
IS61VPS102436A-166TQ-TR	ISSI	获取价格	Standard SRAM, 1MX36, 3.5ns, CMOS, PQFP100
IS61VPS102436B-166B3LI	ISSI	获取价格	IC SRAM 36M PARALLEL 166MHZ
IS61VPS102436B-166B3LI-TR	ISSI	获取价格	IC SRAM 36M PARALLEL 166MHZ
IS61VPS102436B-250B3L	ISSI	获取价格	Cache SRAM, 1MX36, 2.8ns, CMOS, PBGA165, TFBGA-165
IS61VPS102436B-250TQLI	ISSI	获取价格	Cache SRAM, 1MX36, 2.8ns, CMOS, PQFP100, LQFP-100
IS61VPS102436B-250TQLI-TR	ISSI	获取价格	IC SRAM 36M PARALLEL 100LQFP
IS61VPS12832EC-200B2	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS61VPS12832EC-200B2I	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS61VPS12832EC-200B2L	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS61VPS12832EC-200B2LI	ISSI	获取价格	128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM

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