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IS61VPD10018-166TQ PDF预览

IS61VPD10018-166TQ

更新时间： 2024-11-24 14:51:39
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
24页 167K
描述
Cache SRAM, 1MX18, 3.5ns, CMOS, PQFP100, TQFP-100

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IS61VPD10018-166TQ 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：TQFP-100针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.92
最长访问时间：3.5 nsJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：18874368 bit内存集成电路类型：CACHE SRAM
内存宽度：18功能数量：1
端子数量：100字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：1MX18封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：240认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

IS61VPD10018-166TQ 数据手册

 浏览型号IS61VPD10018-166TQ的Datasheet PDF文件第2页浏览型号IS61VPD10018-166TQ的Datasheet PDF文件第3页浏览型号IS61VPD10018-166TQ的Datasheet PDF文件第4页浏览型号IS61VPD10018-166TQ的Datasheet PDF文件第5页浏览型号IS61VPD10018-166TQ的Datasheet PDF文件第6页浏览型号IS61VPD10018-166TQ的Datasheet PDF文件第7页 
IS61VPD51232  
IS61VPD51236  
IS61VPD10018  
®
ISSI  
512K x 32, 512K x 36, 1024K x 18  
SYNCHRONOUS PIPELINED,  
ADVANCEINFORMATION  
MAY 2001  
DOUBLE CYCLE DESELECT STATIC RAM  
DESCRIPTION  
FEATURES  
The ISSI IS61VPD51232, IS61VPD51236, and  
IS61VPD10018 are high-speed, low-power synchronous  
static RAMs designed to provide burstable, high-performance  
memory for communication and networking applications.  
TheIS61VPD51232isorganizedas524,288wordsby32bits  
and the IS61VPD51236 is organized as 524,288 words by  
36 bits. The IS61VPD10018 is organized as 1,048,576  
words by 18 bits. Fabricated with ISSI's advanced CMOS  
technology, the device integrates a 2-bit burst counter,  
high-speed SRAM core, and high-drive capability outputs  
into a single monolithic circuit. All synchronous inputs  
pass through registers controlled by a positive-edge-  
triggered single clock input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Linear burst sequence control using MODE input  
•
Threechipenableoptionforsimpledepthexpansion  
and address pipelining  
• Common data inputs and data outputs  
• JEDEC 100-Pin TQFP and  
119-pin PBGA package  
Write cycles are internally self-timed and are initiated by  
the rising edge of the clock input. Write cycles can be one  
to four bytes wide as controlled by the write control inputs.  
• Single +2.5V, ±5% operation  
• Auto Power-down during deselect  
• Double cycle deselect  
Separate byte enables allow individual bytes to be written.  
Byte write operation is performed by using byte write  
enable (BWE).input combined with one or more individual  
byte write signals (BWx). In addition, Global Write (GW)  
is available for writing all bytes at one time, regardless of  
the byte write controls.  
• Snooze MODE for reduced-power standby  
• JTAG Boundary Scan for PBGA package  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
input pins. Subsequent burst addresses can be generated  
internally and controlled by the ADV (burst address  
advance) input pin.  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW.  
Interleave burst is achieved when this pin is tied HIGH or  
left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-200  
3.1  
5
-166  
3.5  
6
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
ns  
Frequency  
200  
166  
MHz  
This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best  
possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
1
ADVANCE INFORMATION Rev. 00A  
05/31/01  
1234567...24

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与IS61VPD10018-166TQ相关器件

型号 品牌 获取价格 描述 数据表
IS61VPD102418-200TQ ISSI

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 		Cache SRAM, 1MX18, 3.1ns, CMOS, PQFP100, TQFP-100
IS61VPD102418-250B2I ISSI

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 		Cache SRAM, 1MX18, 2.6ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119
IS61VPD102418A ISSI

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 		512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD102418A-200B3 ISSI

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 		512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD102418A-200B3I ISSI

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 		512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD102418A-200TQ ISSI

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 		512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD102418A-200TQI ISSI

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 		512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD102418A-250B3 ISSI

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 		512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD102418A-250B3I ISSI

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 		512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD102418A-250TQ ISSI

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 		512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

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