Datasheet > IS61QDPB451236A-400M3LI

IS61QDPB451236A-400M3LI

更新时间： 2024-02-08 15:19:21

品牌	Logo	应用领域
美国芯成 - ISSI		时钟静态存储器内存集成电路
页数	文件大小	规格书
33页	653K
描述
QDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

IS61QDPB451236A-400M3LI 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	LBGA, BGA165,11X15,40	Reach Compliance Code：	compliant
Factory Lead Time：	10 weeks	风险等级：	5.16
最长访问时间：	0.45 ns	最大时钟频率 (fCLK)：	400 MHz
I/O 类型：	SEPARATE	JESD-30 代码：	R-PBGA-B165
长度：	17 mm	内存密度：	18874368 bit
内存集成电路类型：	QDR SRAM	内存宽度：	36
功能数量：	1	端子数量：	165
字数：	524288 words	字数代码：	512000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	512KX36
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	电源：	1.5/1.8,1.8 V
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最大待机电流：	0.32 A	最小待机电流：	1.7 V
子类别：	SRAMs	最大压摆率：	1 mA
最大供电电压 (Vsup)：	1.89 V	最小供电电压 (Vsup)：	1.71 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	宽度：	15 mm
Base Number Matches：	1

IS61QDPB451236A-400M3LI 数据手册

浏览型号IS61QDPB451236A-400M3LI的Datasheet PDF文件第2页

浏览型号IS61QDPB451236A-400M3LI的Datasheet PDF文件第3页

浏览型号IS61QDPB451236A-400M3LI的Datasheet PDF文件第4页

浏览型号IS61QDPB451236A-400M3LI的Datasheet PDF文件第5页

浏览型号IS61QDPB451236A-400M3LI的Datasheet PDF文件第6页

浏览型号IS61QDPB451236A-400M3LI的Datasheet PDF文件第7页

IS61QDPB41M18A/A1/A2

IS61QDPB451236A/A1/A2

1Mx18, 512Kx36

18Mb QUADP (Burst 4) SYNCHRONOUS SRAM

JANUARY 2013

(2.5 Cycle Read Latency)

FEATURES

DESCRIPTION

The 18Mb IS61QDPB451236A/A1/A2 and



512Kx36 and 1Mx18 configuration available.

IS61QDPB41M18A/A1/A2 are synchronous, high-

performance CMOS static random access memory (SRAM)

devices. These SRAMs have separate I/Os, eliminating the

need for high-speed bus turnaround. The rising edge of K

clock initiates the read/write operation, and all internal

operations are self-timed. Refer to the Timing Reference

Diagram for Truth Table for a description of the basic

operations of these QUADP (Burst of 4) SRAMs. Read and

write addresses are registered on alternating rising edges of

the K clock. Reads and writes are performed in double data

rate.

On-chip Delay-Locked Loop (DLL) for wide data

valid window.



Separate independent read and write ports with

concurrent read and write operations.



Synchronous pipeline read with late write operation.

Double Data Rate (DDR) interface for read and

write input ports.



2.5 cycle read latency.

Fixed 4-bit burst for read and write operations.

Clock stop support.

The following are registered internally on the rising edge of

the K clock:

Two input clocks (K and K#) for address and control

registering at rising edges only.



Read/write address



Two echo clocks (CQ and CQ#) that are delivered

simultaneously with data.

Read enable



Data Valid Pin (QVLD).

Write enable

Byte writes for burst addresses 1 and 3

Data-in for burst addresses 1 and 3

+1.8V core power supply and 1.5, 1.8V VDDQ, used

with 0.75, 0.9V VREF.



HSTL input and output interface.

The following are registered on the rising edge of the K#

clock:

Registered addresses, write and read controls, byte

writes, data in, and data outputs.



Byte writes for burst addresses 2 and 4



Full data coherency.



Data-in for burst addresses 2 and 4

Boundary scan using limited set of JTAG 1149.1

functions.

Byte writes can change with the corresponding data-in to

enable or disable writes on a per-byte basis. An internal write

buffer enables the data-ins to be registered one cycle after

the write address. The first data-in burst is clocked one cycle

later than the write command signal, and the second burst is

timed to the following rising edge of the K# clock. Two full

clock cycles are required to complete a write operation.



Byte write capability.

Fine ball grid array (FBGA) package:

13mmx15mm and 15mmx17mm body size

165-ball (11 x 15) array

Programmable impedance output drivers via 5x

user-supplied precision resistor.



During the burst read operation, the data-outs from the first

and third bursts are updated from output registers of the third

and fourth rising edges of the K# clock (starting 2.5 cycles

later after read command). The data-outs from the second

and fourth bursts are updated with the fourth and fifth rising

edges of the K clock where the read command receives at

the first rising edge of K. Two full clock cycles are required to

complete a read operation.

ODT (On Die Termination) feature is supported

optionally on data input, K/K#, and BW_x#.

The end of top mark (A/A1/A2) is to define options.

IS61QDPB451236A : Don’t care ODT function

and pin connection

IS61QDPB451236A 1 : Option1

IS61QDPB451236A 2 : Option2

Refer to more detail description at page 6 for each

ODT option.

The device is operated with a single +1.8V power supply

and is compatible with HSTL I/O interfaces.

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

1/2/2013

12 3 4 5 6 7...33

中文翻译

下载PDF

与IS61QDPB451236A-400M3LI相关器件

型号	品牌	获取价格	描述	数据表
IS61S6432	ICSI	获取价格	64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61S6432-117PQ	ICSI	获取价格	64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61S6432-117PQ	ISSI	获取价格	64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61S6432-117PQI	ICSI	获取价格	64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61S6432-117PQI	ISSI	获取价格	64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61S6432-117TQ	ISSI	获取价格	64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61S6432-117TQ	ICSI	获取价格	64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61S6432-117TQI	ISSI	获取价格	64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61S6432-117TQI	ICSI	获取价格	64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61S6432-133PQ	ICSI	获取价格	64K x 32 SYNCHRONOUS PIPELINE STATIC RAM

与IS61QDPB451236A-400M3LI相关文章

REF70数据手册解读：高精度电压参考源的全面剖析
2024-07-08

2
解析30211801数据手册：PCB端子排MKDSV 5/3-9.5
2024-07-08

1
UL248-14数据手册深度解读：微型保险丝的全面剖析
2024-07-08

3
BSS138LT3G：一款高效能N沟道MOSFET的全面解析
2024-07-04

18

产品中心

服务支持

精选活动

关于我们

帮助中心

IS61QDPB451236A-400M3LI

IS61QDPB451236A-400M3LI 技术参数

IS61QDPB451236A-400M3LI 数据手册

与IS61QDPB451236A-400M3LI相关器件

与IS61QDPB451236A-400M3LI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IS61QDPB451236A-400M3LI

IS61QDPB451236A-400M3LI 技术参数

IS61QDPB451236A-400M3LI 数据手册

与IS61QDPB451236A-400M3LI相关器件

与IS61QDPB451236A-400M3LI相关文章

您还可以找

您在本页遇到什么问题？