Datasheet > IS41C44002A

IS41C44002A

更新时间： 2022-12-11 22:15:00

品牌	Logo	应用领域
矽成 - ICSI		/
页数	文件大小	规格书
20页	249K
描述
4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

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数据手册

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IS41C44002A 数据手册

IC41C44002A/IC41C44002AS(L)

IC41LV44002A/IC41LV44002AS(L)

AC CHARACTERISTICS (Continued)^{(1,2,3,4,5,6)}

(Recommended Operating Conditions unless otherwise noted.)

-50

-60

Symbol

Parameter

Min. Max.

Units

t^OEH

OE Hold Time from WE during

−

READ-MODIFY-WRITE cycle⁽¹⁸⁾

tDS

Data-In Setup Time^{(15, 22)}

Data-In Hold Time^{(15, 22)}

−

tDH

tRWC

t^RWD

READ-MODIFY-WRITE Cycle Time

108

133

RAS to WE Delay Time during

READ-MODIFY-WRITE Cycle⁽¹⁴⁾

tCWD

tAWD

t^PC

CAS to WE Delay Time^{(14, 20)}

−

Column-Address to WE Delay Time⁽¹⁴⁾

EDO Page Mode READ or WRITE

Cycle Time

tRASP

tCPA

RAS Pulse Width in EDO Page Mode

Access Time from CAS Precharge⁽¹⁵⁾

EDO Page Mode READ-WRITE

Cycle Time

−

100K

−

100K

tPRWC

−

tCOH

tOFF

Data Output Hold after CAS LOW

−

Output Buffer Turn-Off Delay from

(13,15,19, 24)

CAS or RAS

tWHZ

tCSR

tCHR

tRPC

t^ORD

Output Disable Delay from WE

−

CAS Setup Time (CBR REFRESH)^{(20, 25)}

CAS Hold Time (CBR REFRESH)^{( 21, 25)}

RAS to CAS Precharge Time

OE Setup Time prior to RAS during

HIDDEN REFRESH Cycle

tREF

Auto Refresh Period

Transition Time (Rise or Fall)^{(2, 3)}

2,048 Cycles

−

AC TEST CONDITIONS

Output load:

Two TTL Loads and 100 pF (Vcc=5.0V±10%)

One TTL Loads and 100 pF (Vcc=3.3V±10%)

Input timing reference levels: VIH = 2.4V, VIL = 0.8V

Output timing reference levels: VOH = 2.0V, VOL = 0.8V

Integrated Circuit Solution Inc.

DR026-0A 09/04/2001

1...5 6 789 10 11...20

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