Datasheet > IS41C44002A

IS41C44002A

更新时间： 2022-12-11 22:15:00

品牌	Logo	应用领域
矽成 - ICSI		/
页数	文件大小	规格书
20页	249K
描述
4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

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IS41C44002A 数据手册

IC41C44002A/IC41C44002AS(L)

IC41LV44002A/IC41LV44002AS(L)

ELECTRICAL CHARACTERISTICS⁽¹⁾

(Recommended Operating Conditions unless otherwise noted.)

Symbol Parameter

Test Condition

Speed Min. Max.

Unit

I^IL

Input Leakage Current

Any input 0V ≤ VIN ≤ Vcc

Other inputs not under test = 0V

−5

2.4

−

µA

IIO

Output Leakage Current

Output High Voltage Level

Output Low Voltage Level

Standby Current: TTL

Output is disabled (Hi-Z)

0V ≤ VOUT ≤ Vcc

µA

VOH

VOL

ICC1

I^CC2

ICC3

IOH = −5.0 mA with VCC=5V

IOH = −2.0 mA with VCC=3.3V

−

IOL = 4.2 mA with VCC=5V

IOL = 2 mA with VCC=3.3V

0.4

RAS, CAS ≥ VIH

3.3V

−

Standby Current: CMOS

RAS, CAS ≥ VCC − 0.2V

3.3V

−

0.5

OperatingCurrent:

RAS, CAS,

Address Cycling, tRC = tRC (min.)

-50

-60

−

120

110

RandomRead/Write^(2,3,4)

Average Power Supply Current

ICC4

ICC5

ICCS

Operating Current:

RAS = VIL, CAS,

-50

-60

−

µA

EDO Page Mode^(2,3,4)

Cycling tPC = tPC (min.)

Average Power Supply Current

Refresh Current:

RAS, CAS Cycling

tRC = tRC (min.)

-50

-60

−

120

110

CBR^(2,3,5)

Average Power Supply Current

Self Refresh current⁽⁶⁾

Self Refresh Mode

5V,nromal version

5V, L version

500

350

3.3V, normal version

3.3, L version

450

350

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device

operation is assured. The eight RAS cycles wake-up should be repeated any time the t^REFrefresh requirement is exceeded.

2. Dependent on cycle rates.

3. Specified values are obtained with minimum cycle time and the output open.

4. Column-address is changed once each EDO page cycle.

5. Enables on-chip refresh and address counters.

6. I^CCSis for S version only.

Integrated Circuit Solution Inc.

DR026-0A 09/04/2001

1...3 4 567 8 9...20

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