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IS41C4100-35J PDF预览

IS41C4100-35J

更新时间: 2024-02-28 18:55:35
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路光电二极管动态存储器
页数 文件大小 规格书
19页 145K
描述
1Meg x 4 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

IS41C4100-35J 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:TSOP, TSOP20/26,.36Reach Compliance Code:unknown
风险等级:5.83最长访问时间:35 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-G20
JESD-609代码:e0内存密度:4194304 bit
内存集成电路类型:EDO DRAM内存宽度:4
端子数量:20字数:1048576 words
字数代码:1000000最高工作温度:70 °C
最低工作温度:组织:1MX4
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP封装等效代码:TSOP20/26,.36
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
电源:5 V认证状态:Not Qualified
刷新周期:1024自我刷新:NO
最大待机电流:0.001 A子类别:DRAMs
最大压摆率:0.11 mA标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

IS41C4100-35J 数据手册

 浏览型号IS41C4100-35J的Datasheet PDF文件第1页浏览型号IS41C4100-35J的Datasheet PDF文件第2页浏览型号IS41C4100-35J的Datasheet PDF文件第4页浏览型号IS41C4100-35J的Datasheet PDF文件第5页浏览型号IS41C4100-35J的Datasheet PDF文件第6页浏览型号IS41C4100-35J的Datasheet PDF文件第7页 
IS41C4100  
IS41LV4100  
®
ISSI  
TRUTHTABLE  
Function  
RAS  
CAS  
WE  
X
OE Address tR/tC  
I/O  
Standby  
H
L
L
H
L
L
X
L
L
X
High-Z  
Read: Word  
Read: Lower Byte  
H
ROW/COL  
ROW/COL  
DOUT  
H
Lower Byte, DOUT  
Upper Byte, High-Z  
Read: Upper Byte  
L
H
H
L
ROW/COL  
Lower Byte, High-Z  
Upper Byte, DOUT  
Write: Word (Early Write)  
L
L
L
L
L
L
X
X
ROW/COL  
ROW/COL  
DIN  
Write: Lower Byte (Early Write)  
Lower Byte, DIN  
Upper Byte, High-Z  
Write: Upper Byte (Early Write)  
Read-Write(1,2)  
L
H
L
X
ROW/COL  
Lower Byte, High-Z  
Upper Byte, DIN  
L
L
L
HL  
HL  
LH ROW/COL  
DOUT, DIN  
EDO Page-Mode Read(2)  
DOUT  
1st Cycle:  
H
L
ROW/COL  
2nd Cycle:  
Any Cycle:  
L
L
HL  
LH  
H
H
L
L
NA/COL DOUT  
NA/NA DOUT  
EDO Page-Mode Write(1)  
1st Cycle:  
2nd Cycle:  
L
L
HL  
HL  
L
L
X
X
ROW/COL, DIN  
NA/COL DIN  
EDO Page-Mode  
DOUT, DIN  
1st Cycle:  
L
HL  
HL  
LH  
ROW/COL  
Read-Write(1,2)  
2nd Cycle:  
Read  
L
HL  
HL  
LH  
NA/COL DOUT, DIN  
ROW/COL  
Hidden Refresh2)  
DOUT  
LHL  
L
H
L
Write  
LHL  
L
L
X
ROW/COL  
DOUT  
RAS-Only Refresh  
L
H
L
X
X
X
X
ROW/NA  
X
High-Z  
High-Z  
CBR Refresh(3)  
HL  
Notes:  
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).  
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).  
3. At least one of the two CAS signals must be active (LCAS or UCAS).  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
PRELIMINARY INFORMATION Rev. 00A  
3
09/10/01  

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