Datasheet > IQX128B-PQ184

IQX128B-PQ184

更新时间： 2024-01-05 23:27:36

品牌	Logo	应用领域
其他 - ETC		外围集成电路
页数	文件大小	规格书
65页	600K
描述
User Programmable Special Function ASIC

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技术参数
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IQX128B-PQ184 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	PLASTIC, QFP-184	Reach Compliance Code：	unknown
风险等级：	5.92	Is Samacsys：	N
边界扫描：	NO	JESD-30 代码：	S-PQFP-G184
JESD-609代码：	e0	低功率模式：	NO
端子数量：	184	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装形状：	SQUARE	封装形式：	FLATPACK
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
uPs/uCs/外围集成电路类型：	DSP PERIPHERAL, CROSSBAR SWITCH	Base Number Matches：	1

IQX128B-PQ184 数据手册

IQX Family Data Sheet

FEATURES

DESCRIPTION

•

SRAM-based, in-system programmable

Switch Matrix

The IQX family of SRAM-based bit-oriented switching devices is

manufactured using a 0.6µm CMOS process. These devices

offer clock speeds of up to 133 MHz and pin-to-pin delay as low

as 7.5 ns.

— Non-Blocking

— Identical and predictable delays

— One-to-one, one-to-many and many-to-one connections

The IQX devices are used in applications requiring dynamic

switching and flexible routing / interconnection of signals. These

applications include communication switches, network systems,

DSP / image processing engines and file/video servers.

•

RapidConfigure™ parallel interface for fast, incremental

configuration of Switch Matrix and I/O Port attributes

— 100% JTAG compliant

At the heart of IQX devices is a non-blocking Switch Matrix. A

line in the Switch Matrix can be connected to one or more other

lines. The Switch Matrix lines are connected to I/O Ports with

programmable functional attributes.

Clocked, Latched and Flow-through Dataflow Modes

— As low as 7.5 ns pin-to-pin delay in flow-through mode

and 133 MHz clock rate in registered mode

I/O Ports

The RapidConfigure parallel interface allows connections in the

Switch Matrix to be changed quickly and incrementally. This

interface can also be used to configure I/O Port attributes

individually and incrementally. In either case, data integrity is

maintained on all unchanged signal paths through the device.

— Individually programmable as input, output or

bidirectional

— For each I/O Port, clock, clock enable, input enable and

output enable can be selected independently from a large

pool of common control signals

The IQX devices support the industry standard JTAG (IEEE

1149.1) interface for boundary scan testing. The same interface

can also used for serially downloading the configuration bit

stream into the devices.

— 12 mA current drive

— Separated I/O power pins for easy interfacing between

5V and 3.3V signals

Dedicated

I/O Control Signals

Shared with

I/O Control

Signals

I/O Port

I/O

Control

I/O Port

Signal

Ports

Switch Matrix

[Crossbar Array]

I/O Port

Shared with

RapidConfigure

Interface Signals

RapidConfigure

Interface

JTAG Configuration Control

TDO TDI TMS TCK TRST*

Figure 1. IQX Functional Block Diagram

June 2000

Revision 5.0

12 3 4 5 6 7...65

中文翻译

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IQX320-10PP391	ETC	获取价格	User Programmable Special Function ASIC
IQX320-10PP391I	ETC	获取价格	User Programmable Special Function ASIC
IQX320-12PB416	ETC	获取价格	User Programmable Special Function ASIC

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