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IQX160-7PQ208 PDF预览

IQX160-7PQ208

更新时间: 2024-09-26 23:58:47
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65页 600K
描述
User Programmable Special Function ASIC

IQX160-7PQ208 数据手册

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IQX Family Data Sheet  
FEATURES  
DESCRIPTION  
SRAM-based, in-system programmable  
Switch Matrix  
The IQX family of SRAM-based bit-oriented switching devices is  
manufactured using a 0.6µm CMOS process. These devices  
offer clock speeds of up to 133 MHz and pin-to-pin delay as low  
as 7.5 ns.  
Non-Blocking  
Identical and predictable delays  
— One-to-one, one-to-many and many-to-one connections  
The IQX devices are used in applications requiring dynamic  
switching and flexible routing / interconnection of signals. These  
applications include communication switches, network systems,  
DSP / image processing engines and file/video servers.  
RapidConfigure™ parallel interface for fast, incremental  
configuration of Switch Matrix and I/O Port attributes  
— 100% JTAG compliant  
At the heart of IQX devices is a non-blocking Switch Matrix. A  
line in the Switch Matrix can be connected to one or more other  
lines. The Switch Matrix lines are connected to I/O Ports with  
programmable functional attributes.  
Clocked, Latched and Flow-through Dataflow Modes  
As low as 7.5 ns pin-to-pin delay in flow-through mode  
and 133 MHz clock rate in registered mode  
I/O Ports  
The RapidConfigure parallel interface allows connections in the  
Switch Matrix to be changed quickly and incrementally. This  
interface can also be used to configure I/O Port attributes  
individually and incrementally. In either case, data integrity is  
maintained on all unchanged signal paths through the device.  
Individually programmable as input, output or  
bidirectional  
— For each I/O Port, clock, clock enable, input enable and  
output enable can be selected independently from a large  
pool of common control signals  
The IQX devices support the industry standard JTAG (IEEE  
1149.1) interface for boundary scan testing. The same interface  
can also used for serially downloading the configuration bit  
stream into the devices.  
— 12 mA current drive  
— Separated I/O power pins for easy interfacing between  
5V and 3.3V signals  
Dedicated  
I/O Control Signals  
Shared with  
I/O Control  
Signals  
I/O Port  
I/O Port  
I/O  
Control  
I/O Port  
I/O Port  
Signal  
Ports  
Switch Matrix  
[Crossbar Array]  
I/O Port  
I/O Port  
I/O Port  
Shared with  
RapidConfigure  
Interface Signals  
RapidConfigure  
Interface  
JTAG Configuration Control  
TDO TDI TMS TCK TRST*  
Figure 1. IQX Functional Block Diagram  
June 2000  
Revision 5.0  
1
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