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IN74AC573DW PDF预览

IN74AC573DW

更新时间: 2024-10-29 22:48:07
品牌 Logo 应用领域
INTEGRAL 锁存器
页数 文件大小 规格书
5页 221K
描述
Octal 3-State Noninverting Transparent Latch

IN74AC573DW 技术参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:unknown风险等级:5.84

IN74AC573DW 数据手册

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TECHNICAL DATA  
IN74AC573  
Octal 3-State Noninverting  
Transparent Latch  
High-Performance Silicon-Gate CMOS  
The IN74AC573 is identical in pinout to the LS/ALS573,  
HC/HCT573. The device inputs are compatible with standard CMOS  
outputs; with pullup resistors, they are compatible with LS/ALS  
outputs.  
These latches appear transparent to data (i.e., the outputs change  
asynchronously) when Latch Enable is high. When Latch Enable goes  
low, data meeting the setup and hold time becomes latched.  
ORDERING INFORMATION  
IN74AC573N Plastic  
IN74AC573DW SOIC  
TA = -40° to 85° C for all packages  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
Low Input Current: 1.0 µA; 0.1 µA @ 25°C  
High Noise Immunity Characteristic of CMOS Devices  
Outputs Source/Sink 24 mA  
PIN ASSIGNMENT  
LOGIC DIAGRAM  
FUNCTION TABLE  
PIN 20=VCC  
PIN 10 = GND  
Inputs  
Latch  
Output  
Q
Output  
D
Enable Enable  
L
H
H
L
H
L
H
L
L
no change  
Z
L
X
X
H
X
X = don’t care  
Z = high impedance  
456  

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