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IN74AC112D PDF预览

IN74AC112D

更新时间: 2024-11-26 03:44:11
品牌 Logo 应用领域
INTEGRAL 触发器
页数 文件大小 规格书
5页 179K
描述
Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

IN74AC112D 技术参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:unknown风险等级:5.75
Base Number Matches:1

IN74AC112D 数据手册

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TECHNICAL DATA  
IN74AC112  
Dual J-K Flip-Flop  
with Set and Reset  
High-Speed Silicon-Gate CMOS  
The IN74AC112 is identical in pinout to the LS/ALS112,  
HC/HCT112. The device inputs are compatible with standard CMOS  
outputs; with pullup resistors, they are compatible with LS/ALS  
outputs.  
Each flip-flop is negative-edge clocked and has active-low  
asynchronous Set and Reset inputs.  
ORDERING INFORMATION  
IN74AC112N Plastic  
IN74AC112D SOIC  
TA = -40° to 85° C for all  
packages  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
Low Input Current: 1.0 µA; 0.1 µA @ 25°C  
High Noise Immunity Characteristic of CMOS Devices  
Outputs Source/Sink 24 mA  
PIN ASSIGNMENT  
LOGIC DIAGRAM  
FUNCTION TABLE  
Inputs  
Clock  
Outputs  
Set  
L
Reset  
H
J
K
X
X
X
L
Q
Q
L
X
X
X
X
X
X
L
H
L
L*  
H
L
L
H
L*  
L
H
H
H
H
H
H
H
H
No Change  
H
L
H
L
L
H
L
H
H
H
X
X
X
H
H
H
X
X
X
Toggle  
H
L
No Change  
No Change  
No Change  
H
H
H
* Both outputs will remain low as long as Set and Reset are  
low, but the output states are unpredictable if Set and Reset  
go high simultaneously  
PIN 16=VCC  
PIN 8 = GND  
X = Don’t Care  
127  

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